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1. 发明申请

US20120171805A1 METHOD OF FABRICATING A SOLAR CELL 有权
标题翻译：制造太阳能电池的方法
公开(公告)号：US20120171805A1
公开(公告)日：2012-07-05
申请号：US13049886
申请日：2011-03-16
申请人： Yen-Cheng Hu , Cheng-Chang Kuo , Jun-Wei Chen , Hsin-Feng Li , Jen-Chieh Chen , Zhen-Cheng Wu
发明人： Yen-Cheng Hu , Cheng-Chang Kuo , Jun-Wei Chen , Hsin-Feng Li , Jen-Chieh Chen , Zhen-Cheng Wu
IPC分类号： H01L31/18
CPC分类号： H01L31/068 , H01L31/186 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a solar cell is provided. A first type semiconductor substrate having a first surface and a second surface is provided. A second type doped diffusion region is formed in parts of the first type semiconductor substrate. The second type doped diffusion region extends within the first type semiconductor substrate from the first surface. An anti-reflection coating (ARC) in contact with second type doped diffusion region is formed over the first surface. A conductive paste including conductive particles and dopant is formed over the ARC. A co-firing process for enabling the conductive paste to penetrate the ARC to form a first contact conductor embedded in the ARC is performed. During the co-firing process, the dopant diffuses into the second type doped diffusion region and a second type heavily doped diffusion region is formed. A second contact conductor is formed on the second surface.
摘要翻译：提供一种制造太阳能电池的方法。提供具有第一表面和第二表面的第一类型的半导体衬底。在第一类型半导体衬底的部分中形成第二类型的掺杂扩散区。第二类掺杂扩散区从第一表面在第一类型半导体衬底内延伸。在第一表面上形成与第二类掺杂扩散区接触的抗反射涂层（ARC）。在ARC上形成包括导电颗粒和掺杂剂的导电浆料。执行用于使导电浆料穿透ARC以形成嵌入ARC中的第一接触导体的共烧制方法。在共烧制过程中，掺杂剂扩散到第二类掺杂扩散区，形成第二类重掺杂扩散区。第二接触导体形成在第二表面上。

2. 发明授权

US08338217B2 Method of fabricating a solar cell 有权
标题翻译：制造太阳能电池的方法
公开(公告)号：US08338217B2
公开(公告)日：2012-12-25
申请号：US13049886
申请日：2011-03-16
申请人： Yen-Cheng Hu , Cheng-Chang Kuo , Jun-Wei Chen , Hsin-Feng Li , Jen-Chieh Chen , Zhen-Cheng Wu
发明人： Yen-Cheng Hu , Cheng-Chang Kuo , Jun-Wei Chen , Hsin-Feng Li , Jen-Chieh Chen , Zhen-Cheng Wu
IPC分类号： H01L31/18
CPC分类号： H01L31/068 , H01L31/186 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a solar cell is provided. A first type semiconductor substrate having a first surface and a second surface is provided. A second type doped diffusion region is formed in parts of the first type semiconductor substrate. The second type doped diffusion region extends within the first type semiconductor substrate from the first surface. An anti-reflection coating (ARC) in contact with second type doped diffusion region is formed over the first surface. A conductive paste including conductive particles and dopant is formed over the ARC. A co-firing process for enabling the conductive paste to penetrate the ARC to form a first contact conductor embedded in the ARC is performed. During the co-firing process, the dopant diffuses into the second type doped diffusion region and a second type heavily doped diffusion region is formed. A second contact conductor is formed on the second surface.
摘要翻译：提供一种制造太阳能电池的方法。提供具有第一表面和第二表面的第一类型的半导体衬底。在第一类型半导体衬底的部分中形成第二类型的掺杂扩散区。第二类掺杂扩散区从第一表面在第一类型半导体衬底内延伸。在第一表面上形成与第二类掺杂扩散区接触的抗反射涂层（ARC）。在ARC上形成包括导电颗粒和掺杂剂的导电浆料。执行用于使导电浆料穿透ARC以形成嵌入ARC中的第一接触导体的共烧制方法。在共烧制过程中，掺杂剂扩散到第二类掺杂扩散区，形成第二类重掺杂扩散区。第二接触导体形成在第二表面上。

3. 发明授权

US07956437B2 Isolation structures for integrated circuits 有权
公开(公告)号：US07956437B2
公开(公告)日：2011-06-07
申请号：US12455212
申请日：2009-05-28
申请人： Richard K. Williams , Donald Ray Disney , Jun-Wei Chen , Wai Tien Chan , HyungSik Ryu
发明人： Richard K. Williams , Donald Ray Disney , Jun-Wei Chen , Wai Tien Chan , HyungSik Ryu
IPC分类号： H01L21/70
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

4. 发明申请

US20070278612A1 Isolation structures for integrated circuits and modular methods of forming the same 有权
标题翻译：用于集成电路的隔离结构和形成其的模块化方法
公开(公告)号：US20070278612A1
公开(公告)日：2007-12-06
申请号：US11444102
申请日：2006-05-31
申请人： Richard K. Williams , Donald Ray Disney , Jun-Wei Chen , Wai Tien Chan , HyungSik Ryu
发明人： Richard K. Williams , Donald Ray Disney , Jun-Wei Chen , Wai Tien Chan , HyungSik Ryu
IPC分类号： H01L29/00
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.
摘要翻译：用于半导体衬底的各种隔离结构包括形成在衬底中的沟槽，其填充有电介质材料或填充有导电材料并且沿着沟槽的壁衬有介电层。沟槽可以与掺杂的侧壁隔离区域组合使用。沟槽和侧壁隔离区域都可以是环形的并且包围衬底的隔离袋。隔离结构通过不包括显着的热处理或掺杂剂扩散的模块化注入和蚀刻工艺形成，使得所得到的结构是紧凑的并且可以紧密地堆积在衬底的表面中。

5. 发明授权

US5328866A Low temperature oxide layer over field implant mask 失效
标题翻译：场外植入掩模上的低温氧化层
公开(公告)号：US5328866A
公开(公告)日：1994-07-12
申请号：US949288
申请日：1992-09-21
申请人： Mike F. Chang , David G. Grasso , Jun-Wei Chen
发明人： Mike F. Chang , David G. Grasso , Jun-Wei Chen
IPC分类号： H01L21/761 , H01L21/316 , H01L21/32 , H01L21/76 , H01L21/762 , H01L21/8249 , H01L27/06
CPC分类号： H01L21/8249 , H01L21/32 , H01L21/76202 , H01L21/76216
摘要： A thin base oxide is disposed over both an active area and also over a field area of a substrate. A thin silicon-nitride layer is then formed over the base oxide in the active area to protect the underlying substrate from oxygen and/or water vapor during a subsequent field oxidation step. This thin nitride layer is, however, insufficiently thick to serve as a field implant mask in a subsequent field implant step. An additional low temperature oxide (LTO) layer is therefore provided over the nitride layer in the active area. The field implant step is then performed using the base oxide, the thin nitride, and the overlying LTO as a field implant mask. The boundaries of the overlying LTO define a field implant boundary. After the field implant step but before the field oxidation step, the LTO layer is removed from the top of the thin nitride layer. As a result, only the base oxide and the thin nitride layer is disposed over the active area during field oxidation. Therefore, in comparison to previous methods using thicker nitride layers, the present invention employs a thin nitride layer during the field oxidation step, thereby reducing the amount of stress induced in the nitride layer and thereby minimizing problems associated with thick nitride layers such as the introduction of lattice defects into the underlying silicon substrate. The thin nitride process of the present invention may, for example, be incorporated into a BiCDMOS process.
摘要翻译：薄基底氧化物设置在有源区域上以及衬底的场区域上方。然后在有源区域中的基底氧化物上形成薄的氮化硅层，以在随后的场氧化步骤期间保护下面的衬底免受氧气和/或水蒸汽的影响。然而，这种薄的氮化物层在随后的场注入步骤中不足以用作场注入掩模。因此，在活性区域中的氮化物层上提供另外的低温氧化物（LTO）层。然后使用基底氧化物，薄氮化物和上覆的LTO作为场注入掩模来执行场注入步骤。上覆LTO的边界定义了一个场注入边界。在场注入步骤之后但在场氧化步骤之前，从薄氮化物层的顶部去除LTO层。结果，在场氧化期间只有基极氧化物和薄氮化物层设置在有源区上。因此，与使用较厚氮化物层的先前方法相比，本发明在场氧化步骤期间采用薄的氮化物层，从而减少在氮化物层中诱发的应力的量，从而最小化与氮化物层相关的问题，例如导入的晶格缺陷进入下面的硅衬底。本发明的薄氮化物工艺可以例如并入BiCDMOS工艺中。

6. 发明授权

US08659086B2 ESD protection for bipolar-CMOS-DMOS integrated circuit devices 有权
标题翻译：双极CMOS-DMOS集成电路器件的ESD保护
公开(公告)号：US08659086B2
公开(公告)日：2014-02-25
申请号：US12286326
申请日：2008-09-30
申请人： Donald Ray Disney , Jun-Wei Chen , Richard K. Williams , HyungSik Ryu , Wai Tien Chan
发明人： Donald Ray Disney , Jun-Wei Chen , Richard K. Williams , HyungSik Ryu , Wai Tien Chan
IPC分类号： H01L23/62
CPC分类号： H01L29/735 , H01L27/0251 , H01L29/0626 , H01L29/0692 , H01L29/7317 , H01L29/7833 , H01L29/861 , H01L29/866
摘要： An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.
摘要翻译：在半导体衬底的隔离区域中形成静电放电（ESD）保护器件。 ESD保护器件可以是MOS或双极晶体管或二极管的形式。隔离结构可以包括深度植入的地板层和横向围绕隔离区域的一个或多个植入的孔。隔离结构和ESD保护器件使用模块化工艺制造，其中几乎不包括热处理。由于ESD器件是隔离的，所以两个或多个ESD器件可以彼此电“堆叠”，使得器件的触发电压相加在一起以实现更高的有效触发电压。

7. 发明申请

US20090034136A1 ESD protection for bipolar-CMOS-DMOS integrated circuit devices 有权
公开(公告)号：US20090034136A1
公开(公告)日：2009-02-05
申请号：US12286325
申请日：2008-09-30
申请人： Donald Ray Disney , Jun-Wei Chen , Richard K. Williams , HyungSik Ryu , Wai Tien Chan
发明人： Donald Ray Disney , Jun-Wei Chen , Richard K. Williams , HyungSik Ryu , Wai Tien Chan
IPC分类号： H02H9/04
CPC分类号： H01L29/735 , H01L27/0251 , H01L29/0626 , H01L29/0692 , H01L29/7317 , H01L29/7833 , H01L29/861 , H01L29/866
摘要： An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

8. 发明申请

US20080067586A1 High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same 有权
公开(公告)号：US20080067586A1
公开(公告)日：2008-03-20
申请号：US11982781
申请日：2007-11-05
申请人： Richard Williams , Donald Disney , Jun-Wei Chen , Wai Chan , HyungSik Ryu
发明人： Richard Williams , Donald Disney , Jun-Wei Chen , Wai Chan , HyungSik Ryu
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L21/761 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L21/8249 , H01L27/0623 , H01L27/088 , H01L27/098 , H01L29/0696 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66106 , H01L29/66659 , H01L29/66704 , H01L29/66901 , H01L29/7825 , H01L29/7835 , H01L29/808 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.

9. 发明申请

US20080067585A1 High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same 有权
公开(公告)号：US20080067585A1
公开(公告)日：2008-03-20
申请号：US11982764
申请日：2007-11-05
申请人： Richard Williams , Donald Disney , Jun-Wei Chen , Wai Chan , Hyung Ryu
发明人： Richard Williams , Donald Disney , Jun-Wei Chen , Wai Chan , Hyung Ryu
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/761 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L21/8249 , H01L27/0623 , H01L27/088 , H01L27/098 , H01L29/0696 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66106 , H01L29/66659 , H01L29/66704 , H01L29/66901 , H01L29/7825 , H01L29/7835 , H01L29/808 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.

10. 发明申请

US20080029820A1 ESD protection for bipolar-CMOS-DMOS integrated circuit devices and modular method of forming the same 有权
标题翻译：双极CMOS-DMOS集成电路器件的ESD保护及其形成的模块化方法
公开(公告)号：US20080029820A1
公开(公告)日：2008-02-07
申请号：US11499381
申请日：2006-08-04
申请人： Donald Ray Disney , Jun-Wei Chen , Richard K. Williams , HyungSik Ryu , Wai Tien Chan
发明人： Donald Ray Disney , Jun-Wei Chen , Richard K. Williams , HyungSik Ryu , Wai Tien Chan
IPC分类号： H01L23/62
CPC分类号： H01L29/735 , H01L27/0251 , H01L29/0626 , H01L29/0692 , H01L29/7317 , H01L29/7833 , H01L29/861 , H01L29/866
摘要： An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.
摘要翻译：在半导体衬底的隔离区域中形成静电放电（ESD）保护器件。 ESD保护器件可以是MOS或双极晶体管或二极管的形式。隔离结构可以包括深度植入的地板层和横向围绕隔离区域的一个或多个植入的孔。隔离结构和ESD保护器件使用模块化工艺制造，其中几乎不包括热处理。由于ESD器件是隔离的，所以两个或多个ESD器件可以彼此电“堆叠”，使得器件的触发电压相加在一起以实现更高的有效触发电压。

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