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1. 发明授权

US08697520B2 Method of forming an asymmetric poly gate for optimum termination design in trench power MOSFETS 有权
标题翻译：在沟槽功率MOSFET中形成非对称多晶硅栅极以实现最佳端接设计的方法
公开(公告)号：US08697520B2
公开(公告)日：2014-04-15
申请号：US13411422
申请日：2012-03-02
申请人： Yeeheng Lee , Yongping Ding , Xiaobin Wang
发明人： Yeeheng Lee , Yongping Ding , Xiaobin Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L27/088 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
摘要翻译：具有多个晶体管的半导体器件包括具有非对称栅极的晶体管的端接区域。

2. 发明授权

US09627526B2 Assymetric poly gate for optimum termination design in trench power MOSFETs 有权
公开(公告)号：US09627526B2
公开(公告)日：2017-04-18
申请号：US14224043
申请日：2014-03-24
申请人： Yeeheng Lee , Yongping Ding , Xiaobin Wang
发明人： Yeeheng Lee , Yongping Ding , Xiaobin Wang
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L29/7811 , H01L27/088 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

3. 发明申请

US20170069750A9 ASSYMETRIC POLY GATE FOR OPTIMUM TERMINATION DESIGN IN TRENCH POWER MOSFETS 审中-公开
标题翻译：用于TRENCH功率MOSFET的最终终止设计的组合聚合物门
公开(公告)号：US20170069750A9
公开(公告)日：2017-03-09
申请号：US14224043
申请日：2014-03-24
申请人： Yeeheng Lee , Yongping Ding , Xiaobin Wang
发明人： Yeeheng Lee , Yongping Ding , Xiaobin Wang
IPC分类号： H01L29/78 , H01L27/088
CPC分类号： H01L29/7811 , H01L27/088 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
摘要翻译：具有多个晶体管的半导体器件包括具有非对称栅极的晶体管的端接区域。

4. 发明申请

US20130228857A1 METHOD OF FORMING AN ASSYMETRIC POLY GATE FOR OPTIMUM TERMINATION DESIGN IN TRENCH POWER MOSFETS 有权
标题翻译：形成用于TRENCH功率MOSFET中的最终终止设计的组合聚合物门的方法
公开(公告)号：US20130228857A1
公开(公告)日：2013-09-05
申请号：US13411422
申请日：2012-03-02
申请人： Yeeheng Lee , Yongping Ding , Xiaobin Wang
发明人： Yeeheng Lee , Yongping Ding , Xiaobin Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L27/088 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
摘要翻译：具有多个晶体管的半导体器件包括具有非对称栅极的晶体管的端接区域。

5. 发明申请

US20150221734A1 THICKER BOTTOM OXIDE FOR REDUCED MILLER CAPACITANCE IN TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) 审中-公开
标题翻译：用于减少金属氧化物半导体场效应晶体管（MOSFET）的减少半导体电容的厚度底部氧化物
公开(公告)号：US20150221734A1
公开(公告)日：2015-08-06
申请号：US14171777
申请日：2014-02-04
申请人： Yeeheng Lee , Xiaobin Wang
发明人： Yeeheng Lee , Xiaobin Wang
IPC分类号： H01L29/423 , H01L29/51 , H01L29/78 , H01L21/321 , H01L21/28 , H01L21/311 , H01L21/033 , H01L21/02 , H01L29/49 , H01L29/66
摘要： Semiconductor device fabrication method and devices are disclosed. The semiconductor power device is formed on a semiconductor substrate having a plurality of trench transistor cells each having a trench gate. Each of the trench gates having a thicker bottom oxide (TBO) formed by a REOX process on a polysilicon layer deposited on a bottom surface of the trenches.
摘要翻译：公开了半导体器件制造方法和器件。半导体功率器件形成在具有各自具有沟槽栅极的多个沟槽晶体管单元的半导体衬底上。每个沟槽栅极具有较厚的底部氧化物（TBO），其通过REOX工艺在沉积在沟槽的底表面上的多晶硅层上形成。

6. 发明申请

US20150270383A1 ASSYMETRIC POLY GATE FOR OPTIMUM TERMINATION DESIGN IN TRENCH POWER MOSFETS 审中-公开
标题翻译：用于TRENCH功率MOSFET的最终终止设计的组合聚合物门
公开(公告)号：US20150270383A1
公开(公告)日：2015-09-24
申请号：US14224043
申请日：2014-03-24
申请人： Yeeheng Lee , Yongping Dong , Xiaobin Wang
发明人： Yeeheng Lee , Yongping Dong , Xiaobin Wang
IPC分类号： H01L29/78 , H01L27/088
CPC分类号： H01L29/7811 , H01L27/088 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
摘要翻译：具有多个晶体管的半导体器件包括具有非对称栅极的晶体管的端接区域。

7. 发明申请

US20100314682A1 Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions 有权
标题翻译：用于制造具有沟槽氧化物 - 纳米管超结的器件的配置和方法
公开(公告)号：US20100314682A1
公开(公告)日：2010-12-16
申请号：US12661004
申请日：2010-03-05
申请人： Hamza Yilmaz , Madhur Bobde , Yeeheng Lee , Lingpeng Guan , Xiaobin Wang , John Chen , Anup Bhalla
发明人： Hamza Yilmaz , Madhur Bobde , Yeeheng Lee , Lingpeng Guan , Xiaobin Wang , John Chen , Anup Bhalla
IPC分类号： H01L29/78 , H01L21/336 , H01L21/762
CPC分类号： H01L29/7397 , H01L29/0661 , H01L29/66348
摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.
摘要翻译：本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。可以在第一外延层上生长第二外延层。每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。

8. 发明申请

US20110140228A1 Method of Filling Large Deep Trench with High Quality Oxide for Semiconductor Devices 有权
标题翻译：用于半导体器件的高质量氧化物填充大深沟槽的方法
公开(公告)号：US20110140228A1
公开(公告)日：2011-06-16
申请号：US12637988
申请日：2009-12-15
申请人： Xiaobin Wang , Anup Bhalla , Yeeheng Lee
发明人： Xiaobin Wang , Anup Bhalla , Yeeheng Lee
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/0657 , H01L21/76202 , H01L21/76224 , H01L21/76227 , H01L29/407 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.
摘要翻译：公开了一种用于产生具有沟槽尺寸TCS和沟槽深度TCD的具有氧化物填充的大深沟槽（OFLDT）部分的半导体器件结构的方法。体积半导体层（BSL）设置有厚度BSLT> TCD。一个大的沟槽顶部区域（LTTA）映射到BSL顶部，其几何形状等于OFLDT。 LTTA被划分为散置的，互补的临时区域ITA-A和ITA-B。通过去除对应于ITA-B的散装半导体材料，在顶部BSL表面上形成了许多深度TCD的临时垂直沟槽。对应于ITA-A的剩余体积半导体材料被转化为氧化物。如果在经过转换的ITA-A之间仍然留有剩余空间，则剩余空间被氧化物沉积填满。重要的是，所有ITA-A和ITA-B的几何形状都应该被简单而小型化，以便于快速有效地进行氧化物转换和氧化物填充。

9. 发明申请

US20170125531A9 THICKER BOTTOM OXIDE FOR REDUCED MILLER CAPACITANCE IN TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) 审中-公开
公开(公告)号：US20170125531A9
公开(公告)日：2017-05-04
申请号：US14171777
申请日：2014-02-04
申请人： Yeeheng Lee , Xiaobin Wang
发明人： Yeeheng Lee , Xiaobin Wang
IPC分类号： H01L29/423 , H01L29/51 , H01L29/78 , H01L21/321 , H01L21/28 , H01L21/311 , H01L21/033 , H01L21/02 , H01L29/49 , H01L29/66
CPC分类号： H01L29/4236 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/0332 , H01L21/28035 , H01L21/31111 , H01L21/31144 , H01L21/3212 , H01L29/407 , H01L29/42368 , H01L29/4916 , H01L29/51 , H01L29/518 , H01L29/66719 , H01L29/66734 , H01L29/7813
摘要： Semiconductor device fabrication method and devices are disclosed. The semiconductor power device is formed on a semiconductor substrate having a plurality of trench transistor cells each having a trench gate. Each of the trench gates having a thicker bottom oxide (TBO) formed by a REOX process on a polysilicon layer deposited on a bottom surface of the trenches.

10. 发明授权

US08390058B2 Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions 有权
标题翻译：用于制造具有沟槽氧化物 - 纳米管超结的器件的配置和方法
公开(公告)号：US08390058B2
公开(公告)日：2013-03-05
申请号：US12661004
申请日：2010-03-05
申请人： Hamza Yilmaz , Madhur Bobde , Yeeheng Lee , Lingpeng Guan , Xiaobin Wang , John Chen , Anup Bhalla
发明人： Hamza Yilmaz , Madhur Bobde , Yeeheng Lee , Lingpeng Guan , Xiaobin Wang , John Chen , Anup Bhalla
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7397 , H01L29/0661 , H01L29/66348
摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.
摘要翻译：本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。可以在第一外延层上生长第二外延层。每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。

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