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1. 发明授权

US06351369B1 Multi-layer capacitor, wiring substrate, decoupling circuit, and high-frequency circuit 有权
标题翻译：多层电容器，布线基板，去耦电路和高频电路
公开(公告)号：US06351369B1
公开(公告)日：2002-02-26
申请号：US09514516
申请日：2000-02-28
申请人： Yoichi Kuroda , Masaaki Taniguchi , Yasuyuki Naito , Haruo Hori , Takanori Kondo
发明人： Yoichi Kuroda , Masaaki Taniguchi , Yasuyuki Naito , Haruo Hori , Takanori Kondo
IPC分类号： H01G4228
CPC分类号： H01G4/232 , H01G4/30 , H01L23/642 , H01L2924/0002 , H05K1/0231 , H05K2201/10515 , H05K2201/10734 , H01L2924/00
摘要： A multi-layer capacitor achieves significant reduction in equivalent series inductance (ESL) and includes first inner electrodes and second inner electrodes opposing each other, first feed-through conductors and second feed-through conductors, and first outer terminal electrodes and second outer terminal electrodes. The first feed-through conductors electrically connect the first inner electrodes and the first outer terminal electrodes, and the second feed-through conductors electrically connect the second inner electrodes and the second outer terminal electrodes. The first and second feed-through conductors are arranged such that the feed-through conductors mutually cancel magnetic fields induced by current flowing through the first and second inner electrodes. Furthermore, when an alignment pitch of the first and second feed-through conductors is indicated by P and the total number of the first and second feed-through conductors is indicated by N, an arrangement is set such that a ratio of P/N is about 0.085 mm or lower.
摘要翻译：多层电容器实现了等效串联电感（ESL）的显着降低，并且包括彼此相对的第一内部电极和第二内部电极，第一馈通导体和第二馈通导体以及第一外部末端电极和第二外部末端电极。第一馈通导体电连接第一内电极和第一外端子电极，第二馈通导体电连接第二内电极和第二外端子电极。第一和第二馈通导体布置成使得馈通导体相互抵消由流过第一和第二内部电极的电流感应的磁场。此外，当第一和第二馈通导体的对准间距由P表示，并且第一和第二馈通导体的总数由N表示时，设置P / N的比率为约0.085mm以下。

2. 发明授权

US06721153B2 Wiring connection structure of laminated capacitor and decoupling capacitor, and wiring board 有权
公开(公告)号：US06721153B2
公开(公告)日：2004-04-13
申请号：US09983187
申请日：2001-10-23
申请人： Yasuyuki Naito , Masaaki Taniguchi , Yoichi Kuroda , Haruo Hori , Takanori Kondo
发明人： Yasuyuki Naito , Masaaki Taniguchi , Yoichi Kuroda , Haruo Hori , Takanori Kondo
IPC分类号： H02H300
CPC分类号： H01L23/66 , H01G4/30 , H01L23/49822 , H01L2224/05155 , H01L2224/05171 , H01L2224/05568 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/16 , H01L2224/16235 , H01L2924/01068 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15313 , H01L2924/19106 , H01L2924/3011 , H05K1/0231 , H05K1/181 , H05K2201/10515 , H05K2201/10719 , H05K2201/10734 , H01L2924/00014
摘要： An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.

3. 发明授权

US06678145B2 Wiring connection structure of laminated capacitor and decoupling capacitor, and wiring board 有权
标题翻译：层叠电容器和去耦电容器的接线连接结构以及接线板
公开(公告)号：US06678145B2
公开(公告)日：2004-01-13
申请号：US10106383
申请日：2002-03-27
申请人： Yasuyuki Naito , Masaaki Taniguchi , Yoichi Kuroda , Haruo Hori , Takanori Kondo
发明人： Yasuyuki Naito , Masaaki Taniguchi , Yoichi Kuroda , Haruo Hori , Takanori Kondo
IPC分类号： H01G220
CPC分类号： H01L23/66 , H01G4/30 , H01L23/49822 , H01L2224/05155 , H01L2224/05171 , H01L2224/05568 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/16 , H01L2224/16235 , H01L2924/01068 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15313 , H01L2924/19106 , H01L2924/3011 , H05K1/0231 , H05K1/181 , H05K2201/10515 , H05K2201/10719 , H05K2201/10734 , H01L2924/00014
摘要： An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.
摘要翻译：提供一种用于封装具有低ESL值的层叠电容器的装置，并且用于去耦电容器以连接到用于提供MPU的MPU芯片的电源电路。叠层电容器容纳在设置在布线板上的空腔内。电容器包括多个通过多个第一馈通导体连接到第一内部电极的第一外部端子电极和经由多个第二馈通导体连接到第二内部电极的多个第二外部端子电极。设置在电容器主体的第一主表面上的第一外部端子电极连接到基板内的电源的热侧的通孔导体，并且设置在第一和第二主表面上的第二外部端子电极连接到接地通孔导体和基板内的母板。

4. 发明授权

US6038121A Monolithic capacitor 有权
标题翻译：单片电容器
公开(公告)号：US6038121A
公开(公告)日：2000-03-14
申请号：US234385
申请日：1999-01-20
申请人： Yasuyuki Naito , Yoichi Kuroda , Masaaki Taniguchi , Haruo Hori , Takanori Kondo
发明人： Yasuyuki Naito , Yoichi Kuroda , Masaaki Taniguchi , Haruo Hori , Takanori Kondo
IPC分类号： H01G4/30 , H01G2/20 , H01G4/228 , H01G4/232
CPC分类号： H01G4/232
摘要： The present invention is to provide a monolithic capacitor for reducing an equivalent series inductance of a monolithic capacitor. The external terminal electrodes are respectively provided on four corners of the capacitor body. External terminal electrodes can also be provided on the side surfaces of the capacitor body. The first inner electrode is connected to two adjacent external corner terminal electrodes and preferably to the external side terminal electrode. The second inner electrode faces the first electrode through a dielectric layer and is connected to other two adjacent external corner terminal electrodes as well as to the external side terminal electrode. The current flowing through the inner electrodes is directed to a variety of directions, and since the current flow in the corner parts of the inner electrodes is smooth, the magnetic fluxes generated in association with the current are cancelled out, thereby reducing the equivalent series inductance.
摘要翻译：本发明提供一种用于降低单片电容器的等效串联电感的单片电容器。外部端子电极分别设置在电容器主体的四个角上。外部端子电极也可以设置在电容器主体的侧表面上。第一内部电极连接到两个相邻的外部角端子电极，优选地连接到外部侧端子电极。第二内电极通过介电层面对第一电极，并且连接到其他两个相邻的外角端子电极以及外侧端子电极。流过内部电极的电流被引导到各种方向，并且由于内部电极的角部中的电流流动是平滑的，所以与电流相关联地产生的磁通被抵消，从而减小了等效串联电感。

5. 发明授权

US07215531B2 Wiring connection structure of laminated capacitor and decoupling capacitor, and wiring board 有权
标题翻译：层叠电容器和去耦电容器的接线连接结构以及接线板
公开(公告)号：US07215531B2
公开(公告)日：2007-05-08
申请号：US10753004
申请日：2004-01-08
申请人： Yasuyuki Naito , Masaaki Taniguchi , Yoichi Kuroda , Haruo Hori , Takanori Kondo
发明人： Yasuyuki Naito , Masaaki Taniguchi , Yoichi Kuroda , Haruo Hori , Takanori Kondo
IPC分类号： H01G4/228
CPC分类号： H01L23/66 , H01G4/30 , H01L23/49822 , H01L2224/05155 , H01L2224/05171 , H01L2224/05568 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/16 , H01L2224/16235 , H01L2924/01068 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15313 , H01L2924/19106 , H01L2924/3011 , H05K1/0231 , H05K1/181 , H05K2201/10515 , H05K2201/10719 , H05K2201/10734 , H01L2924/00014
摘要： An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.
摘要翻译：提供一种用于封装具有低ESL值的层叠电容器的装置，并且用于去耦电容器以连接到用于提供MPU的MPU芯片的电源电路。叠层电容器容纳在设置在布线板上的空腔内。电容器包括多个通过多个第一馈通导体连接到第一内部电极的第一外部端子电极和经由多个第二馈通导体连接到第二内部电极的多个第二外部端子电极。设置在电容器主体的第一主表面上的第一外部端子电极连接到基板内的电源的热侧的通孔导体，并且设置在第一和第二主表面上的第二外部端子电极连接到接地通孔导体和基板内的母板。

6. 发明授权

US06556420B1 Wiring connection structure of laminated capacitor and decoupling capacitor, and wiring board 有权
公开(公告)号：US06556420B1
公开(公告)日：2003-04-29
申请号：US09584838
申请日：2000-05-31
申请人： Yasuyuki Naito , Masaaki Taniguchi , Yoichi Kuroda , Haruo Hori , Takanori Kondo
发明人： Yasuyuki Naito , Masaaki Taniguchi , Yoichi Kuroda , Haruo Hori , Takanori Kondo
IPC分类号： H01G4228
CPC分类号： H01L23/66 , H01G4/30 , H01L23/49822 , H01L2224/05155 , H01L2224/05171 , H01L2224/05568 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/16 , H01L2224/16235 , H01L2924/01068 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15313 , H01L2924/19106 , H01L2924/3011 , H05K1/0231 , H05K1/181 , H05K2201/10515 , H05K2201/10719 , H05K2201/10734 , H01L2924/00014
摘要： An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.

7. 发明授权

US06327134B1 Multi-layer capacitor, wiring board, and high-frequency circuit 有权
标题翻译：多层电容器，接线板和高频电路
公开(公告)号：US06327134B1
公开(公告)日：2001-12-04
申请号：US09678937
申请日：2000-10-04
申请人： Yoichi Kuroda , Masaaki Taniguchi , Yasuyuki Naito , Haruo Hori , Takanori Kondo , Michihiro Murata
发明人： Yoichi Kuroda , Masaaki Taniguchi , Yasuyuki Naito , Haruo Hori , Takanori Kondo , Michihiro Murata
IPC分类号： H01G4005
CPC分类号： H01G4/232 , H01G4/30 , H01L2224/16227 , H01L2224/16235 , H01L2924/15159 , H01L2924/15311 , H05K1/0231 , H05K1/181
摘要： A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.
摘要翻译：多层电容器包括交替布置在电容器主体的四个侧表面上的第一和第二侧面端子电极。第一和第二主表面端子电极布置在电容器主体的主表面上。在电容器体内彼此相对的第一和第二内部电极在端部分别电连接到第一和第二侧面端子电极，并且还分别电连接到第一和第二主表面端子电极，通过通孔导体。通过这种布置，在多层电容器内流动的电流的方向是多样化的，并且导流通路的长度被缩短以达到非常低的ESL值。

8. 发明授权

US06771484B2 Multi-layer capacitor, wiring board, and high-frequency circuit 有权
公开(公告)号：US06771484B2
公开(公告)日：2004-08-03
申请号：US10443092
申请日：2003-05-22
申请人： Yoichi Kuroda , Masaaki Taniguchi , Yasuyuki Naito , Haruo Hori , Takanori Kondo
发明人： Yoichi Kuroda , Masaaki Taniguchi , Yasuyuki Naito , Haruo Hori , Takanori Kondo
IPC分类号： H01G4228
CPC分类号： H01G4/232 , H01G4/30 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15174 , H05K1/0231 , H05K1/181 , H01L2224/05599
摘要： A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.

9. 发明授权

US06909593B2 Multi-layer capacitor, wiring board, and high-frequency circuit 有权
标题翻译：多层电容器，接线板和高频电路
公开(公告)号：US06909593B2
公开(公告)日：2005-06-21
申请号：US10868951
申请日：2004-06-17
申请人： Yoichi Kuroda , Masaaki Taniguchi , Yasuyuki Naito , Haruo Hori , Takanori Kondo
发明人： Yoichi Kuroda , Masaaki Taniguchi , Yasuyuki Naito , Haruo Hori , Takanori Kondo
IPC分类号： H01G4/12 , H01G4/232 , H01G4/30 , H01L23/12 , H05K1/02 , H05K1/18 , H01G4/228
CPC分类号： H01G4/232 , H01G4/30 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15174 , H05K1/0231 , H05K1/181 , H01L2224/05599
摘要： A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.
摘要翻译：多层电容器包括交替布置在电容器主体的四个侧表面上的第一和第二侧面端子电极。第一和第二主表面端子电极布置在电容器主体的主表面上。在电容器体内彼此相对的第一和第二内部电极在端部分别电连接到第一和第二侧面端子电极，并且还分别电连接到第一和第二主表面端子电极，通过通孔导体。通过这种布置，在多层电容器内流动的电流的方向是多样化的，并且导流通路的长度被缩短以达到非常低的ESL值。

10. 发明授权

US06594136B2 Multi-layer capacitor, wiring board, and high-frequency circuit 有权
公开(公告)号：US06594136B2
公开(公告)日：2003-07-15
申请号：US10073085
申请日：2002-02-12
申请人： Yoichi Kuroda , Masaaki Taniguchi , Yasuyuki Naito , Haruo Hori , Takanori Kondo
发明人： Yoichi Kuroda , Masaaki Taniguchi , Yasuyuki Naito , Haruo Hori , Takanori Kondo
IPC分类号： H01G4228
CPC分类号： H01G4/232 , H01G4/30 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15174 , H05K1/0231 , H05K1/181 , H01L2224/05599
摘要： A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.

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