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    • 6. 发明授权
    • High slew rate differential amplifier circuit
    • 高压摆率差分放大电路
    • US06392485B1
    • 2002-05-21
    • US09663388
    • 2000-09-15
    • Yasuyuki DoiTetsuro Oomori
    • Yasuyuki DoiTetsuro Oomori
    • H03F345
    • H03F3/45219G09G3/3688H03F3/4565H03F3/68H03F2203/45431H03F2203/45448H03F2203/45451
    • It is an object of the present invention to provide a high slew rate differential amplifier circuit that can reduce current consumption while maintaining stability. A P-type MOS sub-current source (6) having a current source circuit including a transistor (M18) having a gate voltage of a P-type MOS output transistor (M15) input to a gate thereof and a constant current source transistor (M17) connected in series with the transistor (M18), the current source circuit being connected in parallel with a constant current source transistor (M1) of a P-type MOS differential input section (1) is combined with an N-type MOS sub-current source (7) including a current source circuit including a transistor (M19) having a gate voltage of an N-type MOS output transistor (M16) input to a gate thereof and a constant current source transistor (M20) connected in series with the transistor (M19), the current source circuit being connected in parallel with a constant current source transistor (M6) of an N-type MOS differential input section (2). To increase a current through the differential input section when a high slew rate is required, the current source circuit including the transistor having the gate voltage of the output transistor input to the gate thereof and the constant current source transistor connected in series with the first transistor is used as a sub-current source for a differential circuit, in order to reduce a steady-state current.
    • 本发明的目的是提供一种可以在保持稳定性的同时降低电流消耗的高压摆率差分放大器电路。 一种具有电流源电路的P型MOS子电流源(6),包括具有输入到其栅极的P型MOS输出晶体管(M15)的栅极电压的晶体管(M18)和恒流源晶体管 M17),与P型MOS差分输入部(1)的恒流源晶体管(M1)并联连接的电流源电路与N型MOS子晶体管(M18)组合, 电流源(7),包括电流源电路,其包括具有输入到其栅极的N型MOS输出晶体管(M16)的栅极电压的晶体管(M19)和与栅极串联连接的恒流源晶体管(M20) 所述晶体管(M19),所述电流源电路与N型MOS差分输入部(2)的恒流源晶体管(M6)并联连接。 为了在需要高压摆率时增加通过差分输入部分的电流,电流源电路包括输入到其栅极的输出晶体管的栅极电压的晶体管和与第一晶体管串联连接的恒流源晶体管 被用作差分电路的子电流源,以便降低稳态电流。
    • 8. 发明申请
    • Charge pump type display drive device
    • 电荷泵型显示驱动装置
    • US20070252791A1
    • 2007-11-01
    • US11790332
    • 2007-04-25
    • Tetsuro Oomori
    • Tetsuro Oomori
    • G09G3/30
    • G09G3/3216G09G3/3283
    • An anode drive circuit is provided for each of organic EL elements constituting one row on a passive display panel. The anode drive circuit includes: a capacitor; two switches for permitting the capacitor to store charge by applying a charge voltage to a high-voltage terminal of the capacitor while holding a low-voltage terminal of the capacitor at a reference voltage; and two switches for permitting the capacitor to release charge stored therein by connecting the high-voltage terminal to an anode of an organic EL element while applying a voltage higher than a light emission threshold voltage of the organic EL element to the low-voltage terminal. The number of times of repetition of charge/discharge of the capacitor within one horizontal time period is controlled so as to control the light emission luminance of the organic EL element according to a data signal.
    • 为无源显示面板上构成一行的有机EL元件提供阳极驱动电路。 阳极驱动电路包括:电容器; 两个开关,用于通过在将电容器的低电压端子保持在参考电压的同时向电容器的高压端子施加充电电压来存储电荷; 以及两个开关,用于通过将高电压端子连接到有机EL元件的阳极,同时将高于有机EL元件的发光阈值电压的电压施加到低电压端子,来允许电容器释放其中存储的电荷。 控制在一个水平时间段内电容器的充电/放电重复次数,以便根据数据信号来控制有机EL元件的发光亮度。
    • 10. 发明申请
    • Output driver and diplay device
    • 输出驱动器和显示设备
    • US20080024397A1
    • 2008-01-31
    • US11878032
    • 2007-07-20
    • Tetsuro OomoriMamoru SeikeJunichi Suenaga
    • Tetsuro OomoriMamoru SeikeJunichi Suenaga
    • G09G3/28H03B1/00
    • G09G3/296G09G2330/028H03K19/018528
    • First and second current sources are turned ON/OFF according to display data. A first input transistor has a source connected to a first potential, a drain connected to a second potential via the first current source, and a gate, the drain and the gate being coupled together. A second input transistor has a source connected to the first potential, a drain connected to the second potential via the second current source, and a gate which receives a gate voltage of the first input transistor. A first output transistor has a source connected to the first potential, a drain, and a gate receiving the drain voltage of the second input transistor. A second output transistor has a source connected to the second potential, a drain connected to the drain of the first output transistor, and a gate which receives a control signal corresponding to the display data.
    • 第一和第二电流源根据显示数据打开/关闭。 第一输入晶体管具有连接到第一电位的源极,经由第一电流源连接到第二电位的漏极,以及栅极,漏极和栅极耦合在一起。 第二输入晶体管具有连接到第一电位的源极,经由第二电流源连接到第二电位的漏极和接收第一输入晶体管的栅极电压的栅极。 第一输出晶体管具有连接到第一电位的源极,漏极和接收第二输入晶体管的漏极电压的栅极。 第二输出晶体管具有连接到第二电位的源极,连接到第一输出晶体管的漏极的漏极和接收对应于显示数据的控制信号的栅极。