专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07205577B2 Group 3-5 compound semiconductor and light emitting diode 有权
标题翻译：第3-5组化合物半导体和发光二极管
公开(公告)号：US07205577B2
公开(公告)日：2007-04-17
申请号：US10162404
申请日：2002-06-05
申请人： Yasushi Iyechika , Yoshihiko Tsuchida , Yoshinobu Ono , Masaya Shimizu
发明人： Yasushi Iyechika , Yoshihiko Tsuchida , Yoshinobu Ono , Masaya Shimizu
IPC分类号： H01L33/00
CPC分类号： H01L33/32 , B82Y20/00 , H01L33/06
摘要： A group 3–5 compound semiconductor comprising an interface of two layers having lattice mismatch, an intermediate layer having a film thickness of 25 nm or more and a quantum well layer, in this order. The compound semiconductor has high crystallinity and high quality, and suitably used for a light emitting diode.
摘要翻译：包括具有晶格失配的两层的界面的组3-5化合物半导体，膜厚度为25nm以上的中间层和量子阱层。化合物半导体具有高结晶度和高质量，并且适用于发光二极管。

2. 发明授权

US06225195B1 Method for manufacturing group III-V compound semiconductor 有权
标题翻译： III-V族化合物半导体的制造方法
公开(公告)号：US06225195B1
公开(公告)日：2001-05-01
申请号：US09127922
申请日：1998-08-03
申请人： Yasushi Iyechika , Yoshinobu Ono , Tomoyuki Takada , Masaya Shimizu
发明人： Yasushi Iyechika , Yoshinobu Ono , Tomoyuki Takada , Masaya Shimizu
IPC分类号： C30B2300
CPC分类号： H01L33/325 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L33/007
摘要： A method for manufacturing a group III-V compound semiconductor represented by the general formula InxGayAlzN (where x+y+z=1, 0≦x≦1, 0≦y≦1, and 0≦z≦1) by metalorganic vapor phase epitaxy method is provided. The group III-V compound semiconductor has a semiconductor layer consisting of a p-type dopant-nondoped layer, and a semiconductor layer including a p-type dopant-doped layer. In the method, a reactor for growing the semiconductor layer consisting of a p-type dopant-nondoped layer and a reactor for doping a p-type dopant are mutually different.
摘要翻译：一种用通式InxGayAlzN（其中x + y + z =1,0,0≤x≤1,0<= y <= 1，0≤z≤1）表示的III-V族化合物半导体的制造方法， 1）通过金属有机气相外延法提供。 III-V族化合物半导体具有由p型掺杂剂非掺杂层构成的半导体层和包含p型掺杂剂掺杂层的半导体层。在该方法中，用于生长由p型掺杂剂非掺杂层组成的半导体层的反应器和用于掺杂p型掺杂剂的反应器是相互不同的。

3. 发明授权

US06716724B1 Method of producing 3-5 group compound semiconductor and semiconductor element 有权
标题翻译：生产3-5组化合物半导体和半导体元件的方法
公开(公告)号：US06716724B1
公开(公告)日：2004-04-06
申请号：US10337287
申请日：2003-01-07
申请人： Yasushi Iyechika , Masaya Shimizu , Yoshinobu Ono
发明人： Yasushi Iyechika , Masaya Shimizu , Yoshinobu Ono
IPC分类号： C30B100
CPC分类号： C30B23/02 , C30B25/02 , C30B25/18 , C30B29/403 , C30B29/406 , H01L21/0242 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02647 , Y10S438/975
摘要： In the method of producing the 3-5 group compound semiconductor carrying out the lateral direction selective growth of the desired GaN type 3-5 group compound-semiconductor layer on this c-plane by the stripe mask formed on the c-plane of the underlying crystal containing a GaN type 3-5 group compound semiconductor, a stripe mask is formed on the underlying crystal such that the direction of the stripe is rotated 0.095° or more and less than 9.6° from direction, and with using this stripe mask, the lateral direction selective growth of the GaN type 3-5 group compound-semiconductor layer is carried out, and a high quality 3-5 group compound-semiconductor layer can be formed on the underlying crystal.
摘要翻译：在通过形成在下面的c面上的条纹掩模来制造在该c面上进行期望的GaN 3-5型化合物半导体层的横向选择性生长的3-5族化合物半导体的方法含有GaN类型3-5组化合物半导体的晶体，在下面的晶体上形成条纹掩模，使得条带的方向从<1-100>方向旋转0.095°以上且小于9.6°，并且使用该条带掩模，进行GaN 3-5型化合物半导体层的横向选择性生长，并且可以在下面的晶体上形成高质量的3-5组化合物半导体层。

4. 发明授权

US06875273B2 Method and system for manufacturing III-V Group compound semiconductor and III-V Group compound semiconductor 失效
标题翻译： III-V族化合物半导体和III-V族化合物半导体的制造方法和系统
公开(公告)号：US06875273B2
公开(公告)日：2005-04-05
申请号：US10145713
申请日：2002-05-16
申请人： Toshihisa Katamine , Yasushi Iyechika , Tomoyuki Takada , Yoshihiko Tsuchida , Masaya Shimizu
发明人： Toshihisa Katamine , Yasushi Iyechika , Tomoyuki Takada , Yoshihiko Tsuchida , Masaya Shimizu
IPC分类号： H01L21/20 , C23C16/44 , C23C16/455 , C30B25/14 , C30B29/40
CPC分类号： C23C16/45565 , C23C16/4411 , C23C16/455 , C23C16/45561 , C23C16/45572 , C23C16/45578 , C23C16/45591 , C30B25/14 , C30B29/40 , C30B29/403 , C30B29/406
摘要： In a semiconductor manufacturing system for manufacturing compound semiconductor by MOCVD, a lead-in member is provided for guiding feed gas supplied from a feed gas supply unit onto the surface of a semiconductor substrate disposed in a reactor, a main body of the lead-in member is constituted as a hollow member to form a feed gas guide passage for conducting the feed gas in an prescribed direction and is formed with multiple orifices, and the feed gas in the feed gas guide passage is jetted from the orifices in a direction perpendicular to the prescribed direction so that the semiconductor substrate is bathed in a feed gas flow of uniform amount jetted from the lead-in member in this manner. Furthermore, a pressure differential produced between the inner side and outer side of the nozzle member enables the feed gas jetted from the nozzle member to flow over the whole surface of the substrate at a uniform flow rate. The multiple feed gases are led to the vicinity of the substrate individually and the blow gas blows the multiple feed gases toward the substrate to favorably from desired thin film crystal.
摘要翻译：在通过MOCVD制造化合物半导体的半导体制造系统中，提供了一种引入构件，用于将从进料气体供应单元供应的进料气体引导到设置在反应器中的半导体基板的表面上，引入件的主体构件构成为中空构件，以形成用于沿预定方向导入进料气体的进料气体引导通道，并且形成有多个孔，并且进料气体引导通道中的进料气体从孔口沿垂直于以使得半导体衬底以这种方式浸入从引入构件喷射的均匀量的进料气体流中。此外，在喷嘴构件的内侧和外侧之间产生的压力差使得从喷嘴构件喷射的进料气体以均匀的流速流过基板的整个表面。多个进料气体被单独地引导到基材附近，并且吹气将多个进料气体朝向基板吹送，以期望从期望的薄膜晶体。

5. 发明授权

US08748756B2 Electric device and production method therefor 有权
标题翻译：电气装置及其制造方法
公开(公告)号：US08748756B2
公开(公告)日：2014-06-10
申请号：US13583169
申请日：2011-03-04
申请人： Kenji Kasahara , Masaya Shimizu , Tomoki Kurata
发明人： Kenji Kasahara , Masaya Shimizu , Tomoki Kurata
IPC分类号： H01L23/28
CPC分类号： H01L51/5246 , H01L27/3276 , H01L27/3288 , H01L51/448 , H05B33/0896 , Y02E10/549 , Y02P70/521 , Y10T29/49002
摘要： An electric device includes a support substrate 12, an electric circuit 14 provided in a sealing region set on the support substrate 12, an electric wiring provided on the support substrate 12 for electrically connecting an external electrical signal input/output source with the electric circuit 14, a sealing member 16 provided on the support substrate 12 to surround the sealing region, and a sealing substrate 17 bonded to the support substrate 12 with the sealing member 16 interposed therebetween. the electric circuit 14 includes an electronic element 24 having an organic layer, and a width of the sealing member 16 differs between an intersection region in which the electric wiring 15 and the sealing member 16 intersect each other and a non-intersection region excluding the intersection region.
摘要翻译：电气装置包括支撑基板12，设置在设置在支撑基板12上的密封区域中的电路14，设置在支撑基板12上用于将外部电信号输入/输出源与电路14电连接的电线设置在支撑基板12上以围绕密封区域的密封构件16，以及密封基板17，其密封构件16插入在支撑基板12上。电路14包括具有有机层的电子元件24，并且密封构件16的宽度在电布线15和密封构件16相交的交叉区域与不相交的非交叉区域之间不同地区。

6. 发明申请

US20060022308A1 Group III-V compound semiconductor and method for producing the same 失效
标题翻译： III-V族化合物半导体及其制造方法
公开(公告)号：US20060022308A1
公开(公告)日：2006-02-02
申请号：US11140236
申请日：2005-05-27
申请人： Masaya Shimizu , Shinichi Morishima , Makoto Sasaki
发明人： Masaya Shimizu , Shinichi Morishima , Makoto Sasaki
IPC分类号： H01L29/12
CPC分类号： C30B25/02 , C30B25/18 , C30B29/403 , H01L21/0237 , H01L21/02458 , H01L21/02513 , H01L21/0254 , H01L21/02573 , H01L21/0262 , H01L33/007
摘要： A Group III-V compound semiconductor includes, at least, a substrate, a buffer layer of the general formula InuGavAlwN (wherein, 0≦u≦1, 0≦v≦1, 0≦w≦1, u+v+w=1) and a Group III-V compound semiconductor crystal layer of the general formula InxGayAlzN (wherein, 0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), in this order, wherein the buffer layer has a thickness of at least about 5 Å and not more than about 90 Å. A method is provided for producing the Group III-V compound semiconductor, including forming a buffer layer of the general formula InuGavAlwN on a substrate to give a thickness of at least about 5 Å and not more than about 90 Å at temperatures lower than the growing temperature of the compound semiconductor crystal layer before growing the compound semiconductor crystal layer, and then growing a Group III-V compound semiconductor crystal layer of the general formula InxGayAlzN on the buffer layer.
摘要翻译： III-V族化合物半导体至少包括基底，通式为AlN的缓冲层（其中，0≤u≤1,0<=v≤1,0<= w <= 1，u + v + w = 1）和通式为In的III-V族化合物半导体晶体层（其中，0≤x≤1,0<= y <=1,0.0≤z <= 1，x + y + z = 1），其中缓冲层具有至少约和不大于约的厚度。提供了用于制备III-V族化合物半导体的方法，包括形成通式为III-V族化合物半导体的缓冲层， N，在生长化合物半导体晶体层之前，在比化合物半导体晶体层的生长温度低的温度下，给出至少约不小于约90的厚度，然后生长III-V族在缓冲层上具有通式为Al x Ga y Al y Al z的化合物半导体晶体层。

7. 发明授权

US07754515B2 Compound semiconductor and method for producing same 有权
标题翻译：化合物半导体及其制造方法
公开(公告)号：US07754515B2
公开(公告)日：2010-07-13
申请号：US10558427
申请日：2004-05-28
申请人： Masaya Shimizu , Makoto Sasaki , Yoshihiko Tsuchida
发明人： Masaya Shimizu , Makoto Sasaki , Yoshihiko Tsuchida
IPC分类号： H01L33/00 , H01L21/20
CPC分类号： H01L33/32
摘要： A group III-V compound semiconductor comprising a single quantum well structure which has two barrier layers and a quantum well layer represented by the formula: InxGayAlzN (wherein x+y+z=1, 0
摘要翻译：包括具有两个阻挡层的单量子阱结构的组III-V族化合物半导体和由下式表示的量子阱层：In x Ga y Al z N（其中x + y + z = 1,0

8. 发明授权

US07167237B2 Test system for optical line which carries out fault search for optical line from user optical terminal side 失效
标题翻译：用户光端机进行光线故障检测的光线测试系统
公开(公告)号：US07167237B2
公开(公告)日：2007-01-23
申请号：US10524067
申请日：2004-06-28
申请人： Masaya Shimizu , Hiroaki Endo , Takashi Sakamoto
发明人： Masaya Shimizu , Hiroaki Endo , Takashi Sakamoto
IPC分类号： G01N21/00
CPC分类号： G01M11/3154 , G01M11/3136 , H04B10/071
摘要： A fault searching system searches for a fault in an optical line connected with an optical fiber carrying out data transmission between a transmission apparatus and a user optical terminal. A connecting unit detaches a terminal portion of the optical line at the user optical terminal, and connects an OTDR to the terminal portion of the optical line. At least one of a test light with a wavelength different from a wavelength of light used for data transmission in the optical line, and a test light whose peak level is less than or equal to a predetermined level, is caused to be incident upon the terminal portion of the optical line. A searching unit searches for a fault in the optical line from the user optical terminal side by detecting backward scattering light or return light from the optical line produced by the test light caused by the OTDR.
摘要翻译：故障搜索系统在与发送装置和用户光学终端之间进行数据传输的光纤连接的光线路中寻找故障。连接单元将用户光学终端处的光线路的终端部分分离，并将OTDR连接到光线路的终端部分。在光线路中用于数据传输的光波长不同的测试光和峰值电平小于或等于预定电平的测试光中的至少一个被入射到终端部分光路。搜索单元通过检测由OTDR引起的由测试光产生的光线路的反向散射光或返回光，从用户光学终端侧检索光线路中的故障。

9. 发明授权

US07659190B2 Method for producing a Group III-V compound semiconductor 失效
标题翻译： III-V族化合物半导体的制造方法
公开(公告)号：US07659190B2
公开(公告)日：2010-02-09
申请号：US11140236
申请日：2005-05-27
申请人： Masaya Shimizu , Shinichi Morishima , Makoto Sasaki
发明人： Masaya Shimizu , Shinichi Morishima , Makoto Sasaki
IPC分类号： H01L21/28 , H01L21/3205
CPC分类号： C30B25/02 , C30B25/18 , C30B29/403 , H01L21/0237 , H01L21/02458 , H01L21/02513 , H01L21/0254 , H01L21/02573 , H01L21/0262 , H01L33/007
摘要： A Group III-V compound semiconductor includes, at least, a substrate, a buffer layer of the general formula InuGavAlwN (wherein, 0≦u≦1, 0≦v≦1, 0≦w≦1, u+v+w=1) and a Group III-V compound semiconductor crystal layer of the general formula InxGayAlzN (wherein, 0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), in this order, wherein the buffer layer has a thickness of at least about 5 Å and not more than about 90 Å. A method is provided for producing the Group III-V compound semiconductor, including forming a buffer layer of the general formula InuGavAlwN on a substrate to give a thickness of at least about 5 Å and not more than about 90 Å at temperatures lower than the growing temperature of the compound semiconductor crystal layer before growing the compound semiconductor crystal layer, and then growing a Group III-V compound semiconductor crystal layer of the general formula InxGayAlzN on the buffer layer.
摘要翻译： III-V族化合物半导体至少包括基底，通式为InuGavAlwN的缓冲层（其中，0≤u≤1,0<= v <= 1,0 <= w <= 1， u + v + w = 1）和通式为In x Ga y Al z N的III-V族化合物半导体晶体层（其中，0≤x≤1,0≤y≤1,0≤z≤1， x + y + z = 1），其中缓冲层具有至少约和不大于约的厚度。提供了用于制备III-V族化合物半导体的方法，包括在基底上形成通式为InuGavAlwN的缓冲层，以在比生长的温度低的温度下产生至少约和不大于约的厚度在化合物半导体晶体层生长之前的化合物半导体晶体层的温度，然后在缓冲层上生长通式为In x Ga y Al z N的III-V族化合物半导体晶体层。

10. 发明申请

US20090008745A1 Nitride Compound Semiconductor and Process for Producing the Same 审中-公开
标题翻译：氮化物复合半导体及其制造方法
公开(公告)号：US20090008745A1
公开(公告)日：2009-01-08
申请号：US11658865
申请日：2005-07-28
申请人： Kenji Kasahara , Makoto Sasaki , Masaya Shimizu
发明人： Kenji Kasahara , Makoto Sasaki , Masaya Shimizu
IPC分类号： H01L29/06 , H01L21/205
CPC分类号： H01L33/007 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L33/02 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： A process for producing a nitride compound semiconductor represented by a general formula, InxGayAlzN (where x+y+Z=1, 0≦x≦1, 0≦y≦1, and 0≦z≦1), characterized in that a non-doped nitride compound semiconductor (A) represented by a general formula, InaGabAlcN (where a+b+c=1, 0≦a≦1, 0≦b≦1, and 0≦c≦1) of a thickness of 500 to 5000 Å is formed between a p-type contact layer and an n-type contact layer at a temperature within a range between 550 and 850° C.
摘要翻译：一种由通式InxGayAlzN（其中x + y + Z =1,0,0≤i≤1,0<= z <= 1）表示的氮化物化合物半导体的制造方法，其特征在于，由通式InaGabAlcN（其中a + b + c = 1,0 <= a <= 1,0,0 <= b <= 1，0 <= 1）表示的非掺杂氮化物化合物半导体（A）在550和850℃之间的温度下，在p型接触层和n型接触层之间形成厚度为500至5000的厚度= c <= 1。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式