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1. 发明授权

US5872389A Semiconductor device having a fuse layer 失效
标题翻译：具有熔丝层的半导体器件
公开(公告)号：US5872389A
公开(公告)日：1999-02-16
申请号：US672867
申请日：1996-06-28
申请人： Yasumasa Nishimura , Keiko Ito , Hiroyuki Takeoka , Masanao Maruta , Masaharu Moriyasu
发明人： Yasumasa Nishimura , Keiko Ito , Hiroyuki Takeoka , Masanao Maruta , Masaharu Moriyasu
IPC分类号： H01L21/82 , H01L23/525 , H01L27/10 , H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： Burst pressure P of an insulating layer positioned immediately on a fuse layer is defined by using planar width W of fuse layer and thickness t of insulating layer. The value of the planar width W of fuse layer and the value of the thickness t of insulating layer are set such that the value of burst pressure P is at most about 1000 kg/cm.sup.2. The value of the thickness t and the value of the planar width W are set such that the value t/W is at least 0.45 and at most 0.91. Consequently, stable fuse blowing becomes possible while reducing manufacturing cost.
摘要翻译：通过使用熔丝层的平面宽度W和绝缘层的厚度t来定义紧靠在熔丝层上的绝缘层的爆破压力P. 熔丝层的平面宽度W的值和绝缘层的厚度t的值被设定为使得爆破压力P的值为至多约1000kg / cm 2。厚度t的值和平面宽度W的值被设定为使得值t / W为至少0.45且至多为0.91。因此，可以在降低制造成本的同时实现稳定的熔断器熔断。

2. 发明授权

US08723998B2 Solid-state image pickup device 有权
标题翻译：固态图像拾取装置
公开(公告)号：US08723998B2
公开(公告)日：2014-05-13
申请号：US13542442
申请日：2012-07-05
申请人： Masanao Maruta , Mitsuo Magane
发明人： Masanao Maruta , Mitsuo Magane
IPC分类号： H04N5/378
CPC分类号： H04N5/374 , H03M1/0624 , H03M1/123 , H03M1/56 , H04N5/378
摘要： A solid-state image pickup device includes plural pixels, a voltage generator that generates a reference voltage, plural comparators that are aligned in one direction, and compare respective voltages output from the pixels with the reference voltage, a counter that counts in tandem with a change in the reference voltage generated by the voltage generator, plural buffer circuits that are connected in series with the counter, and each sequentially receives an output of the counter; plural latch circuits that take in a value input to an input terminal thereof according to respective trigger signals output from the comparators, a common signal line that is commonly connected to respective inputs of the latch circuits, and plural signal lines that are connected to respective outputs of the buffer circuits, and allow the output of the counter to propagate therethrough.
摘要翻译：固体摄像装置包括多个像素，产生参考电压的电压发生器，在一个方向上排列的多个比较器，并将来自像素的各个电压与参考电压进行比较，计数器与由电压发生器产生的参考电压的变化，与计数器串联连接的多个缓冲电路，并且每个依次接收计数器的输出; 多个锁存电路根据从比较器输出的各自的触发信号，输入到其输入端的值，共同连接到锁存电路的各个输入的公共信号线，以及连接到各个输出的多个信号线的缓冲电路，并且允许计数器的输出通过其传播。

3. 发明授权

US06885235B2 Semiconductor integrated circuit device with internal power supply potential generation circuit 失效
标题翻译：具有内部电源电位生成电路的半导体集成电路器件
公开(公告)号：US06885235B2
公开(公告)日：2005-04-26
申请号：US10095080
申请日：2002-03-12
申请人： Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
发明人： Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C29/06 , G05F3/04
CPC分类号： G11C5/147
摘要： An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.
摘要翻译：内部电源电位产生电路包括连接到内部电源节点的过充电防止电路。过充电防止电路包括输出由内部电源电位确定的待确定信号的电路，放大要确定的信号之间的电位差和作为输出到节点的参考电位的差分放大电路作为信号表示应该绘制电流，并且响应于指示应当绘制电流的信号，从内部电源节点抽出电流的电流绘制电路。因此，感兴趣的半导体集成电路器件可以提供稳定的内部电源电位。

4. 发明授权

US06466509B1 Semiconductor memory device having a column select line transmitting a column select signal 失效
标题翻译：具有发送列选择信号的列选择线的半导体存储器件
公开(公告)号：US06466509B1
公开(公告)日：2002-10-15
申请号：US10050131
申请日：2002-01-18
申请人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C11/4087 , G11C2207/104
摘要： First and second memory banks are provided with M memory blocks each having first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands arranged on opposite sides of each memory block, and have first and second select lines arranged therefor to select the first and second memory regions, respectively, the first select line being connected to an odd-numbered sense amplifier band of the first memory bank and an even-numbered sense amplifier band of the second memory bank, the second select line being connected to an even-numbered sense amplifier band of the first memory bank and an odd-numbered sense amplifier band of the second memory bank.
摘要翻译：第一和第二存储体设置有M个存储块，每个存储块具有第一和第二存储区域，M表示偶数个不少于两个，以及（M + 1）个读出放大器频带，其布置在每个存储块的相对侧上，并具有第一选择线和第二选择线分别用于选择第一和第二存储区，第一选择线连接到第一存储体的奇数读出放大器带和第二存储体的偶数读出放大器带第二选择线连接到第一存储体的偶数读出放大器带和第二存储体的奇数读出放大器带。

5. 发明授权

US06411560B1 Semiconductor memory device capable of reducing leakage current flowing into substrate 失效
标题翻译：能够减少流入基板的漏电流的半导体存储器件
公开(公告)号：US06411560B1
公开(公告)日：2002-06-25
申请号：US09987277
申请日：2001-11-14
申请人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
IPC分类号： G11C514
CPC分类号： G11C7/1096 , G11C5/146 , G11C5/147 , G11C7/1078 , G11C7/22 , G11C8/10 , G11C11/4074
摘要： A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is [1], a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage≦third power supply voltage+threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.
摘要翻译：第一电源电压被提供给读出放大器的电源节点。位线驱动器将由第二电源电压组成的列选择信号输出到GIO线路电路的N沟道MOS晶体管的栅极端子。当输入/输出数据为[1]时，低于第一电源电压的第三电源电压被提供给全局数据线。在这种情况下，利用所使用的N沟道MOS晶体管的阈值电压，建立关系：第二电源电压<=第三电源电压+阈值电压。结果，在由具有不同电压电平的多个电源电压驱动的半导体存储器件中，可以减小泄漏电流。

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