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1. 发明申请

US20080247227A1 SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF 失效
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20080247227A1
公开(公告)日：2008-10-09
申请号：US12053395
申请日：2008-03-21
申请人： Yasuko TONOMURA , Satoshi KATAGIRI , Yukio Fuji
发明人： Yasuko TONOMURA , Satoshi KATAGIRI , Yukio Fuji
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/08 , G11C7/1042 , G11C11/005 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA1) and (SA2) connected to these transfer lines, respectively; and a control circuit making the sense amplifier (SA2) perform a converting operation during an amplifying operation performed by the sense amplifier (SA1). Because the plural sense amplifiers are allocated to the same bit lines, and these are operated in parallel in this way, data can be read at a high speed.
摘要翻译：半导体存储器件包括：分别与多个存储单元相连的多个位线; 多个传输线共同分配给多个位线; 读取放大器（SA 1）和（SA 2）分别连接到这些传输线; 以及使读出放大器（SA2）在由读出放大器（SA 1）执行的放大操作期间执行转换操作的控制电路。因为将多个读出放大器分配给相同的位线，并且这些以这种方式并行操作，所以可以高速读取数据。

2. 发明申请

US20100085804A1 SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME 有权
标题翻译：半导体存储器件和包括其的数据处理系统
公开(公告)号：US20100085804A1
公开(公告)日：2010-04-08
申请号：US12572699
申请日：2009-10-02
申请人： Satoshi KATAGIRI , Kenji MAE
发明人： Satoshi KATAGIRI , Kenji MAE
IPC分类号： G11C11/00 , G11C8/00 , G11C7/00
CPC分类号： G11C8/12 , G11C7/08 , G11C8/18
摘要： In synchronism with an active command, a row address and a column address are simultaneously received, and a page address is received in synchronism with a read command or a write command. Word drivers select a word line based on the row address, and column switches select a bit line based on the column address. A page address decoder selects any one of read/write amplifiers corresponding to each page based on the page address. With this configuration, a specification for a DRAM such as an access cycle can be satisfied without arranging an amplifier for each bit line, and thus it becomes possible to secure a compatibility with a DRAM while reducing a chip area.
摘要翻译：与活动命令同步，同时接收行地址和列地址，并且与读命令或写命令同步地接收页地址。字驱动程序根据行地址选择字线，列开关根据列地址选择位线。页面地址解码器基于页面地址选择与每个页面相对应的读/写放大器中的任何一个。利用这种配置，可以满足诸如访问周期的DRAM的规范，而不需要为每个位线布置放大器，因此可以在减小芯片面积的同时确保与DRAM的兼容性。

3. 发明申请

US20080278997A1 SEMICONDUCTOR MEMORY DEVICE AND WRITE CONTROL METHOD THEREOF 失效
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20080278997A1
公开(公告)日：2008-11-13
申请号：US12116580
申请日：2008-05-07
申请人： Satoshi KATAGIRI
发明人： Satoshi KATAGIRI
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/1072 , G11C7/1096 , G11C7/22 , G11C13/0004 , G11C13/0061
摘要： A semiconductor memory device comprise a word line, a bit line intersecting the word line, a memory element arranged at intersections of the word line and the bit line and having different required time for a write operation according to a logical value of write data, a write driver supplying a write current to the bit line, a write control circuit controlling operations of the write driver, and a timing signal generation circuit supplying a timing signal to the write control circuit. The timing signal has a waveform including a pulse indicating a time of starting supplying the write current when a first logical level is to be written, a pulse indicating a time of ending supplying the write current if the first logical level is to be written, and a pulse indicating one of a time of starting supplying the write current and a time of ending supplying the write current when a second logical level is to be written.
摘要翻译：半导体存储器件包括字线，与字线相交的位线，布置在字线和位线的交点处的存储元件，并且根据写入数据的逻辑值具有不同的写入操作所需的时间，向位线提供写入电流的写入驱动器，控制写入驱动器的操作的写入控制电路以及向写入控制电路提供定时信号的定时信号产生电路。定时信号具有波形，该波形包括当要写入第一逻辑电平时指示开始提供写入电流的时间的脉冲，指示如果要写入第一逻辑电平则提供写入电流的结束时间的脉冲;以及指示在写入第二逻辑电平时开始提供写入电流的时间中的一个和结束提供写入电流的时间的脉冲。

4. 发明申请

US20130058154A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130058154A1
公开(公告)日：2013-03-07
申请号：US13602544
申请日：2012-09-04
申请人： Satoshi KATAGIRI , Kenji MAE
发明人： Satoshi KATAGIRI , Kenji MAE
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0002 , G11C29/021 , G11C29/028 , G11C29/24 , G11C29/50008 , G11C2029/5004
摘要： A semiconductor device includes a plurality of first memory cells, at least one of second memory cells, and a control circuit. The plurality of first memory cells are accessed during normal operation, wherein the first memory cell includes a first variable resistance element. The second memory cell is not accessed during the normal operation but accessed at a time of test operation. The second memory cell includes a second variable resistance element practically identical to the first variable resistance element. The control circuit performs forming on the second memory cell at the time of the test operation.
摘要翻译：半导体器件包括多个第一存储单元，第二存储单元和控制电路中的至少一个。多个第一存储单元在正常操作期间被访问，其中第一存储单元包括第一可变电阻元件。第二个存储单元在正常操作期间不被访问，但在测试操作时被访问。第二存储单元包括实质上与第一可变电阻元件相同的第二可变电阻元件。控制电路在测试操作时在第二存储单元上进行形成。

5. 发明申请

US20080112218A1 SEMICONDUCTOR MEMORY DEVICE AND WRITE CONTROL METHOD THEREOF 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20080112218A1
公开(公告)日：2008-05-15
申请号：US11872516
申请日：2007-10-15
申请人： Satoshi KATAGIRI
发明人： Satoshi KATAGIRI
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/02
摘要： A semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory elements arranged at intersecting points between the word lines and the bit lines, respectively, a row selector selectively activating the word lines, a plurality of write drivers provided to correspond to the bit lines, and supplying a write current to the corresponding bit lines, respectively, a plurality of write control circuits controlling operations performed by the corresponding write drivers, respectively, and a column selector selecting the write control circuits. The column selector sequentially selects a predetermined write control circuit per one clock in a state of activating a predetermined word line, and the selected write control circuit activates one corresponding write driver over a period of one clock or more.
摘要翻译：半导体存储器件分别包括多个字线，多个位线，分别布置在字线和位线之间的交叉点处的多个存储器元件，选择性地激活字线的行选择器，多个写入驱动器分别对应于位线，并分别向对应的位线提供写入电流，分别控制由对应的写入驱动器执行的操作的多个写入控制电路以及选择写入控制电路的列选择器。列选择器在激活预定字线的状态下每一时钟依次选择预定的写入控制电路，并且所选择的写入控制电路在一个或更多个时钟周期内激活一个对应的写入驱动器。

6. 发明申请

US20110192502A1 Zinc Base Alloy 有权
标题翻译：锌基合金
公开(公告)号：US20110192502A1
公开(公告)日：2011-08-11
申请号：US13021049
申请日：2011-02-04
申请人： Koukichi TAKAHASHI , Satoshi KATAGIRI
发明人： Koukichi TAKAHASHI , Satoshi KATAGIRI
IPC分类号： C22C18/04
CPC分类号： C22C18/02 , C22C18/00 , C22C18/04
摘要： Provided is a zinc base alloy having high strength, and being excellent in toughness and abrasion resistance. The zinc base alloy comprises 3.5% by weight or more and 4.5% by weight or less of Al, 3.0% by weight or more and 4.0% by weight or less of Cu, 0.01% by weight or more and 0.08% by weight or less of Mg, 0.005% by weight or more and 0.1% by weight or less of Ca, and, as necessary, 0.005% by weight or more and 0.1% by weight or less of Sr, and balance of Zn and inevitable impurities. Also provided is a die-cast product made from the zinc base alloy.
摘要翻译：提供一种具有高强度，韧性和耐磨性优异的锌基合金。锌基合金包含3.5重量％以上且4.5重量％以下的Al，3.0重量％以上且4.0重量％以下的Cu，0.01重量％以上且0.08重量％以下的Mg，0.005重量％以上，0.1重量％以下的Ca，必要时为0.005重量％以上且0.1重量％以下，其余为Zn和不可避免的杂质。还提供了由锌基合金制成的压铸产品。

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