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1. 发明授权

US08344458B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08344458B2
公开(公告)日：2013-01-01
申请号：US13110630
申请日：2011-05-18
申请人： Yasuki Yoshihisa , Kikuo Kato , Tetsuya Nitta , Kazuma Onishi
发明人： Yasuki Yoshihisa , Kikuo Kato , Tetsuya Nitta , Kazuma Onishi
IPC分类号： H01L23/62
CPC分类号： H01L21/76224 , H01L21/823481 , H01L27/0251 , H01L27/088
摘要： There is provided a semiconductor device capable of suppressing malfunction of an element to be protected, caused by electrons from an output element into a semiconductor substrate. The semiconductor device is provided with the semiconductor substrate, the output element, the element to be protected, a tap part, and a first active-barrier structure. The first active-barrier structure is disposed between the element to be protected and the tap part. Further, the first active-barrier structure includes an n-type region joined with a p-type doped region, and a p-type region in ohmic coupling with the n-type region.
摘要翻译：提供一种半导体器件，其能够抑制从输出元件到半导体衬底的电子引起的被保护元件的故障。半导体器件设置有半导体衬底，输出元件，要保护的元件，抽头部件和第一有源屏障结构。第一主动阻挡结构设置在待保护元件与抽头部件之间。此外，第一有源屏障结构包括与p型掺杂区域连接的n型区域和与n型区域欧姆耦合的p型区域。

2. 发明授权

US08704330B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08704330B2
公开(公告)日：2014-04-22
申请号：US13305418
申请日：2011-11-28
申请人： Yasuki Yoshihisa , Tetsuya Nitta
发明人： Yasuki Yoshihisa , Tetsuya Nitta
IPC分类号： H01L27/06 , H01L27/088
CPC分类号： H01L27/088 , H01L21/823481 , H01L27/0248
摘要： The semiconductor device includes: a semiconductor substrate; a pair of injection elements; an active barrier structure; and a p-type ground region. The semiconductor substrate has a main surface and a p-type region formed therein. The active barrier structure is arranged in a region sandwiched between the pair of injection elements over the main surface. The p-type ground region is a ground potential-applicable region which is formed closer to an end side of the main surface than the pair of injection elements and the active barrier structure, bypassing a region sandwiched between the pair of injection elements over the main surface, and which is electrically coupled to the p-type region. The p-type ground region is divided by a region adjacent to the region sandwiched between the pair of injection elements.
摘要翻译：半导体器件包括：半导体衬底; 一对注射元件; 主动屏障结构; 和p型接地区域。半导体衬底具有形成在其中的主表面和p型区域。主动屏障结构布置在主表面上夹在该对注入元件之间的区域中。所述p型接地区域是形成为比所述一对注入元件和所述有源势垒结构更接近所述主面的端侧的接地电位适用区域，所述区域绕着所述一对注入元件之间夹在所述主体表面，并且其电耦合到p型区域。 p型接地区域被夹在一对注入元件之间的区域相邻的区域划分。

3. 发明申请

US20070166969A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070166969A1
公开(公告)日：2007-07-19
申请号：US11623473
申请日：2007-01-16
申请人： Shinichiro YANAGI , Yoshitaka Otsu , Takayuki Igarashi , Yasuki Yoshihisa
发明人： Shinichiro YANAGI , Yoshitaka Otsu , Takayuki Igarashi , Yasuki Yoshihisa
IPC分类号： H01L21/425
CPC分类号： H01L27/0629 , H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/823892
摘要： The invention provides a semiconductor device capable of protecting a low-concentration implantation region from contamination, and a method for manufacturing the same. A photoresist is formed on a TEOS film which is formed all over a substrate, and removed by photo engraving so as to be partially left. This photo resist is of a positive or negative type opposite to a type of a photoresist used for formation of a p-offset region and a diffusion region. Then, the TEOS film is etched back except for a portion just under the photoresist. Thereby, a contamination protective film is formed just under the photoresist, and a side wall is formed on a side face of a gate electrode.
摘要翻译：本发明提供能够保护低浓度注入区域免受污染的半导体器件及其制造方法。在TEOS膜上形成光致抗蚀剂，TEOS膜形成在整个基板上，并通过照相雕刻被去除，以便部分留下。该光致抗蚀剂是与用于形成p偏移区域和扩散区域的光致抗蚀剂类型相反的正或负型。然后，除了正好在光致抗蚀剂下面的部分之外，TEOS膜被回蚀刻。由此，在光刻胶的正下方形成污染保护膜，在栅电极的侧面形成有侧壁。

4. 发明授权

US06984868B2 Semiconductor device having a structure for isolating elements 失效
标题翻译：具有用于隔离元件的结构的半导体器件
公开(公告)号：US06984868B2
公开(公告)日：2006-01-10
申请号：US09908611
申请日：2001-07-20
申请人： Yasuki Yoshihisa
发明人： Yasuki Yoshihisa
IPC分类号： H01L29/00
CPC分类号： H01L21/8249 , H01L21/761 , H01L21/76202 , H01L21/763
摘要： A semiconductor device is disclosed involving a semiconductor substrate which contains a buried layer of a predetermined conductivity type as well as trenches deep enough to penetrate through the buried layer for element isolation purposes. Each of the trenches is formed in a boundary area between two regions with a potential difference developing therebetween, and an open-potential area is formed along the trench in the boundary area. This structure prevents leaks from occurring in areas interposed typically between an NPN region and an NMOS region in a BiCMOS semiconductor device, or any other area between two regions subject to two different potential levels.
摘要翻译：公开了一种半导体器件，其包括半导体衬底，该半导体衬底包含预定导电类型的掩埋层以及深度足以穿透掩埋层的沟槽以用于元件隔离目的。每个沟槽形成在两个区域之间的边界区域中，其间形成有电位差，并且沿边界区域中的沟槽形成开放电位区域。这种结构防止在BiCMOS半导体器件中的NPN区域和NMOS区域之间的区域，或者处于两个不同电位水平的两个区域之间的任何其它区域中的区域中发生泄漏。

5. 发明授权

US06440787B1 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06440787B1
公开(公告)日：2002-08-27
申请号：US09598465
申请日：2000-06-22
申请人： Yasuki Yoshihisa
发明人： Yasuki Yoshihisa
IPC分类号： H01L218238
CPC分类号： H01L21/8249
摘要： A manufacturing method of a semiconductor device which can form high-performance bipolar transistors and high-performance MOS transistors on the same substrate while minimizing increases in the number of manufacturing steps and the number of masks. A base lead-out electrode 105a of an NPN bipolar transistor and the gate 105b of a PMOS transistor can be formed at the same time by using the same material (a polysilicon film 105), and an emitter lead-out electrode 122a of the NPN bipolar transistor and the gate 122b of an NMOS transistor are formed at the same time by using the same material (a polysilicon film 122). Therefore, a surface channel PMOS transistor can be obtained while an increase in the number of manufacturing steps is prevented. As a result, the leak current of the PMOS transistor can be reduced and the threshold voltage Vth can be controlled easily.
摘要翻译：一种半导体器件的制造方法，其可以在同一基板上形成高性能双极晶体管和高性能MOS晶体管，同时最小化制造步骤数量和掩模数量。可以通过使用相同的材料（多晶硅膜105）和NPN的发射极引出电极122a同时形成NPN双极晶体管的基极引出电极105a和PMOS晶体管的栅极105b 双极晶体管和NMOS晶体管的栅极122b通过使用相同的材料（多晶硅膜122）同时形成。因此，可以在防止制造步骤数量增加的同时获得表面沟道PMOS晶体管。结果，可以减小PMOS晶体管的泄漏电流，并且可以容易地控制阈值电压Vth。

6. 发明授权

US6051873A Semiconductor device including self-aligned base and emitter electrodes 失效
标题翻译：半导体器件包括自对准的基极和发射极
公开(公告)号：US6051873A
公开(公告)日：2000-04-18
申请号：US7169
申请日：1998-01-14
申请人： Yasuki Yoshihisa
发明人： Yasuki Yoshihisa
IPC分类号： H01L21/28 , H01L21/331 , H01L21/768 , H01L29/73 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66272 , H01L29/7322
摘要： An oxide film mask 6b of a desired shape is formed on the surface of a polysilicon film 5a which becomes a base electrode and the top of the polysilicon film 5a is isotropically etched with the mask 6b, then the polysilicon film 5a is anisotropically etched with the same mask 6b for exposing an epitaxial layer 3.
摘要翻译：在形成基极的多晶硅膜5a的表面上形成所需形状的氧化物膜掩模6b，并且用掩模6b各向同性地蚀刻多晶硅膜5a的顶部，然后将多晶硅膜5a各向异性地蚀刻用于暴露外延层3的相同掩模6b。

7. 发明授权

US5693543A Method of manufacturing a semiconductor IIL device with dielectric and diffusion isolation 失效
标题翻译：制造具有电介质和扩散隔离的半导体IIL器件的方法
公开(公告)号：US5693543A
公开(公告)日：1997-12-02
申请号：US540372
申请日：1995-11-17
申请人： Yasuki Yoshihisa , Masaaki Ikegami
发明人： Yasuki Yoshihisa , Masaaki Ikegami
IPC分类号： H01L27/082 , H01L21/8224 , H01L21/8226 , H01L27/02 , H01L21/265
CPC分类号： H01L21/8224 , H01L27/0237
摘要： n type epitaxial layers are formed on the main surface of a p type semiconductor substrate. A field oxide film is selectively formed in the surface of n type epitaxial layers. An n type diffusion region is formed in n type epitaxial layers positioned directly under field oxide film. A base region and a collector region are respectively formed in the surface of n type epitaxial layer positioned between field oxide films. As a result, a semiconductor device having an IIL circuit is obtained which can suppress the parasitic bipolar operation between base regions, reduce the junction capacitance between the base region and the emitter region and which can be reduced in size.
摘要翻译： n型外延层形成在p型半导体衬底的主表面上。在n型外延层的表面上选择性地形成场氧化膜。在直接位于场氧化膜下方的n型外延层中形成n型扩散区。在位于场氧化膜之间的n型外延层的表面分别形成基极区域和集电极区域。结果，获得了具有IIL电路的半导体器件，其可以抑制基极区域之间的寄生双极性操作，从而减小了基极区域和发射极区域之间的结电容并且可以减小其尺寸。

8. 发明授权

US06562704B2 Method for manufacturing semiconductor device, and semiconductor device 失效
公开(公告)号：US06562704B2
公开(公告)日：2003-05-13
申请号：US10071188
申请日：2002-02-11
申请人： Yasuki Yoshihisa
发明人： Yasuki Yoshihisa
IPC分类号： H01L21425
CPC分类号： H01L22/20
摘要： After introducing an impurity into a polysilicon semiconductor film formed on a substrate, heat treatment is carried out under the conditions not to activate the implanted impurity. The thickness of the polysilicon film and the sheet resistance after introducing the impurity are measured, and the conditions of forming the semiconductor film are adjusted so that the product of the thickness and the sheet resistance is always constant.

9. 发明授权

US5893759A Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5893759A
公开(公告)日：1999-04-13
申请号：US622641
申请日：1996-03-27
申请人： Tatsuhiko Ikeda , Shunji Kubo , Masao Yamawaki , Yasuki Yoshihisa
发明人： Tatsuhiko Ikeda , Shunji Kubo , Masao Yamawaki , Yasuki Yoshihisa
IPC分类号： H01L29/73 , H01L21/265 , H01L21/331 , H01L29/10 , H01L29/732 , H01L21/00
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/7322 , H01L21/26586
摘要： A depression having a depth not exceeding 0.1 .mu.m is formed on the surface of an epitaxial layer. An internal base region is formed just below the depression. An external base region is formed outside the depression. The depression having the above depth can suppress electric field at the end of the internal base in the neighborhood of the junction between the internal base region and the external base region.
摘要翻译：在外延层的表面上形成深度不超过0.1μm的凹陷。在凹陷下方形成内部基部区域。在凹部外形成外部基部区域。具有上述深度的凹陷可以抑制在内部基极区域和外部基极区域之间的接合附近的内部基底的端部处的电场。

10. 发明授权

US5481130A Semiconductor IIL device with dielectric and diffusion isolation 失效
标题翻译：具有介电和扩散隔离的半导体IIL器件
公开(公告)号：US5481130A
公开(公告)日：1996-01-02
申请号：US264119
申请日：1994-06-22
申请人： Yasuki Yoshihisa , Masaaki Ikegami
发明人： Yasuki Yoshihisa , Masaaki Ikegami
IPC分类号： H01L27/082 , H01L21/8224 , H01L21/8226 , H01L27/02 , H01L29/732 , H01L29/735
CPC分类号： H01L21/8224 , H01L27/0237
摘要： n type epitaxial layers are formed on the main surface of a p type semiconductor substrate. A field oxide film is selectively formed in the surface of n type epitaxial layers. An n type diffusion region is formed in n type epitaxial layers positioned directly under field oxide film. A base region and a collector region are respectively formed in the surface of n type epitaxial layer positioned between field oxide films. As a result, a semiconductor device having an IIL circuit is obtained which can suppress the parasitic bipolar operation between base regions, reduce the junction capacitance between the base region and the emitter region and which can be reduced in size.
摘要翻译： n型外延层形成在p型半导体衬底的主表面上。在n型外延层的表面上选择性地形成场氧化膜。在直接位于场氧化膜下方的n型外延层中形成n型扩散区。在位于场氧化膜之间的n型外延层的表面分别形成基极区域和集电极区域。结果，获得了具有IIL电路的半导体器件，其可以抑制基极区域之间的寄生双极性操作，从而减小了基极区域和发射极区域之间的结电容并且可以减小其尺寸。

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