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1. 发明申请

US20070255872A1 BUS SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：总线系统和半导体集成电路
公开(公告)号：US20070255872A1
公开(公告)日：2007-11-01
申请号：US11780031
申请日：2007-07-19
申请人： Yasuhiro TAWARA , Junichi Nishimoto
发明人： Yasuhiro TAWARA , Junichi Nishimoto
IPC分类号： G06F13/00
CPC分类号： G06F13/404
摘要： A technology for allowing easy handling of a change in the address range of the subject of access or any of bus masters is provided. There is provided an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information that has been preset in correspondence to the subject of access and to address information corresponding thereto and capable of determining, by referencing the table, the presence or absence of an access right for each of the bus masters based on the subject-of-access information of each of the bus masters and on address information outputted from the bus master. Since the table is shared among the plurality of bus masters, when the address range of the subject of access or any of the bus masters is changed, the table may be rewritten appropriately. This allows, when a plurality of bus masters are connected to a common bus, easy handling of a change in the address range of the subject of access or any of the bus masters.
摘要翻译：提供了一种允许容易地处理访问主体的地址范围或任何总线主机的改变的技术。提供了一种地址监视器单元，包括在多个总线主机之间共享的表，其中存储对应于访问对象预先设置的访问权限信息和与其对应的地址信息，并且能够通过参考基于每个总线主机的访问主体信息以及从总线主机输出的地址信息，每个总线主机的访问权限的存在或不存在。由于在多个总线主机之间共享表，当访问对象的地址范围或任何总线主机的地址范围改变时，可以适当地重写表。这允许当多个总线主机连接到公共总线时，容易地处理访问对象的地址范围的变化或任何总线主控器。

2. 发明授权

US07263565B2 Bus system and integrated circuit having an address monitor unit 有权
标题翻译：总线系统和具有地址监视器单元的集成电路
公开(公告)号：US07263565B2
公开(公告)日：2007-08-28
申请号：US11213795
申请日：2005-08-30
申请人： Yasuhiro Tawara , Junichi Nishimoto
发明人： Yasuhiro Tawara , Junichi Nishimoto
IPC分类号： G06F13/00 , G06F13/36 , G06F17/00 , G06F13/40
CPC分类号： G06F13/404
摘要： A bus system for handling changes in an access address range of a subject-of-access or a bus master is disclosed. The bus system can have an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information. By referencing the table, the presence or absence of an access right for each of the bus masters can be determined. The table may be rewritten as appropriate to handle address range changes.
摘要翻译：公开了一种用于处理访问主体或总线主机的访问地址范围的变化的总线系统。总线系统可以具有包括在多个总线主机之间共享的表的存储权限信息的地址监视器单元。通过参考该表，可以确定每个总线主机的访问权限的存在或不存在。可以适当地重写表以处理地址范围更改。

3. 发明申请

US20060080485A1 Bus system and semiconductor integrated circuit 有权
标题翻译：总线系统和半导体集成电路
公开(公告)号：US20060080485A1
公开(公告)日：2006-04-13
申请号：US11213795
申请日：2005-08-30
申请人： Yasuhiro Tawara , Junichi Nishimoto
发明人： Yasuhiro Tawara , Junichi Nishimoto
IPC分类号： G06F13/00
CPC分类号： G06F13/404
摘要： A technology for allowing easy handling of a change in the address range of the subject of access or any of bus masters is provided. There is provided an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information that has been preset in correspondence to the subject of access and to address information corresponding thereto and capable of determining, by referencing the table, the presence or absence of an access right for each of the bus masters based on the subject-of-access information of each of the bus masters and on address information outputted from the bus master. Since the table is shared among the plurality of bus masters, when the address range of the subject of access or any of the bus masters is changed, the table may be rewritten appropriately. This allows, when a plurality of bus masters are connected to a common bus, easy handling of a change in the address range of the subject of access or any of the bus masters.
摘要翻译：提供了一种允许容易地处理访问主体的地址范围或任何总线主机的改变的技术。提供了一种地址监视器单元，包括在多个总线主机之间共享的表，其中存储对应于访问对象预先设置的访问权限信息和与其对应的地址信息，并且能够通过参考基于每个总线主机的访问主体信息以及从总线主机输出的地址信息，每个总线主机的访问权限的存在或不存在。由于在多个总线主机之间共享表，当访问对象的地址范围或任何总线主机的地址范围改变时，可以适当地重写表。这允许当多个总线主机连接到公共总线时，容易地处理访问对象的地址范围的变化或任何总线主控器。

4. 发明授权

US07975077B2 Data processing system and data processor 有权
标题翻译：数据处理系统和数据处理器
公开(公告)号：US07975077B2
公开(公告)日：2011-07-05
申请号：US12470988
申请日：2009-05-22
申请人： Junichi Nishimoto , Takuichiro Nakazawa , Koji Yamada , Toshihiro Hattori
发明人： Junichi Nishimoto , Takuichiro Nakazawa , Koji Yamada , Toshihiro Hattori
IPC分类号： G06F13/38
CPC分类号： G06F1/32 , G06F1/325 , G06F1/3265 , G06F9/4403 , G06F9/4416 , G06F13/24 , G06F13/4022 , G06F13/4027 , G06F13/4045 , G06F13/4068 , Y02D10/14 , Y02D10/151
摘要： One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.
摘要翻译：一个数据处理器设置有用于实现与其他数据处理器的连接的接口。该接口具有将作为总线主机的其他数据处理器连接到一个数据处理器的内部总线的功能，并且相关的其他数据处理器能够直接从存储器映射到内部总线的外围功能外部通过接口。因此，数据处理器可以利用其他数据处理器的外围功能，而不中断执行的程序。简而言之，一个数据处理器可以共同使用其他数据处理器的外围资源。

5. 发明授权

US07939692B2 Catalyst and process for producing ketone using the same 失效
标题翻译：催化剂和使用其制备酮的方法
公开(公告)号：US07939692B2
公开(公告)日：2011-05-10
申请号：US12087312
申请日：2007-01-03
申请人： Roger Gläser , Sudhir Dapurkar , Carsten Stöcker , Junichi Nishimoto , Masayoshi Murakami
发明人： Roger Gläser , Sudhir Dapurkar , Carsten Stöcker , Junichi Nishimoto , Masayoshi Murakami
IPC分类号： C07C45/34
CPC分类号： B01J23/44 , B01J27/188 , B01J29/0308 , B01J29/041 , B01J35/0006 , C07C45/34 , C07C49/403
摘要： There are disclosed a method for producing a ketone compound, which comprises reacting an olefin compound with molecular oxygen and water in the presence of an effective amount of proton and a catalyst containing i) a chlorine-free palladium source, ii) a heteropoly acid or an acid salt of a heteropoly acid, and iii) a mesoporous silicate, and catalysts for the process.
摘要翻译：公开了一种生产酮化合物的方法，该方法包括在有效量的质子存在下使烯烃化合物与分子氧和水反应，所述催化剂含有i）无氯钯源，ii）杂多酸或杂多酸的酸性盐，和iii）介孔硅酸盐，以及该方法的催化剂。

6. 发明授权

US07725616B2 Data processing system and data processor 有权
标题翻译：数据处理系统和数据处理器
公开(公告)号：US07725616B2
公开(公告)日：2010-05-25
申请号：US12155412
申请日：2008-06-04
申请人： Junichi Nishimoto , Takuichiro Nakazawa , Koji Yamada , Toshihiro Hattori
发明人： Junichi Nishimoto , Takuichiro Nakazawa , Koji Yamada , Toshihiro Hattori
IPC分类号： G06F13/38
CPC分类号： G06F1/32 , G06F1/325 , G06F1/3265 , G06F9/4403 , G06F9/4416 , G06F13/24 , G06F13/4022 , G06F13/4027 , G06F13/4045 , G06F13/4068 , Y02D10/14 , Y02D10/151
摘要： One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.
摘要翻译：一个数据处理器设置有用于实现与其他数据处理器的连接的接口。该接口具有将作为总线主机的其他数据处理器连接到一个数据处理器的内部总线的功能，并且相关的其他数据处理器能够直接从存储器映射到内部总线的外围功能外部通过接口。因此，数据处理器可以利用其他数据处理器的外围功能，而不中断执行的程序。简而言之，一个数据处理器可以共同使用其他数据处理器的外围资源。

7. 发明授权

US07479823B2 Multiple circuit blocks with interblock control and power conservation 有权
标题翻译：具有互阻控制和省电的多电路块
公开(公告)号：US07479823B2
公开(公告)日：2009-01-20
申请号：US11340488
申请日：2006-01-27
申请人： Tadashi Hoshi , Kenji Hirose , Hideaki Abe , Junichi Nishimoto , Midori Nagayama
发明人： Tadashi Hoshi , Kenji Hirose , Hideaki Abe , Junichi Nishimoto , Midori Nagayama
IPC分类号： G11C5/14
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , H01L2924/0002 , Y02D10/171 , Y02D50/20 , H01L2924/00
摘要： A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.
摘要翻译：提供一种半导体集成电路，其包括多个电路块，并且适于切断对任何一个电路块的电源电压的供应。集成电路包括设置在选通的电路块和信号路径分支到不同分支路径的分支点之间的信号路径上的块间接口电路，以便连接到其他电路块。所述帧间接口电路包括用于防止从所选择的电路块到其他电路块的信号传输的信号门，并且包括用于在电源切断之前存储信号的存储单元。

8. 发明申请

US20060282730A1 Semiconductor integrated circuit incorporating test configuration and test method for the same 失效
标题翻译：半导体集成电路结合测试配置和测试方法相同
公开(公告)号：US20060282730A1
公开(公告)日：2006-12-14
申请号：US11397899
申请日：2006-04-05
申请人： Masayuki Arai , Kazuhiko Iwasaki , Satoshi Fukumoto , Takeshi Shoda , Junichi Nishimoto
发明人： Masayuki Arai , Kazuhiko Iwasaki , Satoshi Fukumoto , Takeshi Shoda , Junichi Nishimoto
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： An object of the invention is to drastically reduce the area overhead in a semiconductor integrated circuit incorporating a test configuration that uses a partially rotational scan circuit. To achieve this, in the semiconductor integrated circuit incorporating the test configuration that comprises a combinational circuit (3) and a scan chain (2) constructed by connecting a plurality of scan flip-flops (5) in a chain, the scan chain (2) is divided into a plurality of sub scan-chains (20a to 20n) each of which has a partially rotational scan (PRS) function and a test response compaction (MISR) function. By performing a scan test in a plurality of steps while changing the combination of the sub scan-chains to be set as PRS and the sub scan-chains to be set as MISR, the test can be performed without having to provide a test response compactor separately from the scan chain, and thus the area overhead can be reduced.
摘要翻译：本发明的一个目的是大大减少包含使用部分旋转扫描电路的测试配置的半导体集成电路中的面积开销。为了实现这一点，在包括组合电路（3）和通过连接多个扫描触发器（5）构成的扫描链（2）的测试配置的半导体集成电路中，扫描链（2））被分成多个子扫描链（20a至20n），每个子扫描链具有部分旋转扫描（PRS）功能和测试响应压缩（MISR）功能。通过在将要设置为PRS的子扫描链和将被设置为MISR的副扫描链的组合改变的同时执行多个步骤中的扫描测试，可以执行测试而不必提供测试响应压缩器与扫描链分开，因此可以减少面积开销。

9. 发明申请

US20050104653A1 Multiple circuit blocks with interblock control and power conservation 有权
标题翻译：具有互阻控制和省电的多电路块
公开(公告)号：US20050104653A1
公开(公告)日：2005-05-19
申请号：US11015649
申请日：2004-12-20
申请人： Tadashi Hoshi , Kenji Hirose , Hideaki Abe , Junichi Nishimoto , Midori Nagayama
发明人： Tadashi Hoshi , Kenji Hirose , Hideaki Abe , Junichi Nishimoto , Midori Nagayama
IPC分类号： H01L21/822 , G06F1/32 , H01L27/04 , H03K19/00 , H03K19/0175 , H03K3/02 , G05F1/10
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , H01L2924/0002 , Y02D10/171 , Y02D50/20 , H01L2924/00
摘要： A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.
摘要翻译：提供一种半导体集成电路，其包括多个电路块，并且适于切断对任何一个电路块的电源电压的供应。集成电路包括设置在从被选择的电路块到其它电路块的信号路径上的互阻止接口电路，其中，将块间接口电路的单个输出分支到其他电路块。帧间接口电路包括用于防止信号传输到其他电路块的信号门，并且包括用于在断电之前存储信号的存储单元。

10. 发明授权

US06389523B1 Cache memory employing dynamically controlled data array start timing and a microprocessor using the same 失效
标题翻译：使用动态控制的数据阵列启动定时的高速缓存存储器和使用其的微处理器
公开(公告)号：US06389523B1
公开(公告)日：2002-05-14
申请号：US09557220
申请日：2000-04-25
申请人： Yasuhisa Shimazaki , Seiichi Nagata , Katuhiro Norisue , Koichiro Ishibashi , Junichi Nishimoto , Shinichi Yoshioka , Susumu Narita
发明人： Yasuhisa Shimazaki , Seiichi Nagata , Katuhiro Norisue , Koichiro Ishibashi , Junichi Nishimoto , Shinichi Yoshioka , Susumu Narita
IPC分类号： G06F1206
CPC分类号： G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A comparator is constituted such that a hit signal &phgr;hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.
摘要翻译：构成一个比较器，使命中信号phihit是高的，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个错误时，命中信号变低。当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。这种新颖的结构实现了高速缓存操作。当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

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