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1. 发明申请

US20060282730A1 Semiconductor integrated circuit incorporating test configuration and test method for the same 失效
标题翻译：半导体集成电路结合测试配置和测试方法相同
公开(公告)号：US20060282730A1
公开(公告)日：2006-12-14
申请号：US11397899
申请日：2006-04-05
申请人： Masayuki Arai , Kazuhiko Iwasaki , Satoshi Fukumoto , Takeshi Shoda , Junichi Nishimoto
发明人： Masayuki Arai , Kazuhiko Iwasaki , Satoshi Fukumoto , Takeshi Shoda , Junichi Nishimoto
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： An object of the invention is to drastically reduce the area overhead in a semiconductor integrated circuit incorporating a test configuration that uses a partially rotational scan circuit. To achieve this, in the semiconductor integrated circuit incorporating the test configuration that comprises a combinational circuit (3) and a scan chain (2) constructed by connecting a plurality of scan flip-flops (5) in a chain, the scan chain (2) is divided into a plurality of sub scan-chains (20a to 20n) each of which has a partially rotational scan (PRS) function and a test response compaction (MISR) function. By performing a scan test in a plurality of steps while changing the combination of the sub scan-chains to be set as PRS and the sub scan-chains to be set as MISR, the test can be performed without having to provide a test response compactor separately from the scan chain, and thus the area overhead can be reduced.
摘要翻译：本发明的一个目的是大大减少包含使用部分旋转扫描电路的测试配置的半导体集成电路中的面积开销。为了实现这一点，在包括组合电路（3）和通过连接多个扫描触发器（5）构成的扫描链（2）的测试配置的半导体集成电路中，扫描链（2））被分成多个子扫描链（20a至20n），每个子扫描链具有部分旋转扫描（PRS）功能和测试响应压缩（MISR）功能。通过在将要设置为PRS的子扫描链和将被设置为MISR的副扫描链的组合改变的同时执行多个步骤中的扫描测试，可以执行测试而不必提供测试响应压缩器与扫描链分开，因此可以减少面积开销。

2. 发明授权

US07702979B2 Semiconductor integrated circuit incorporating test configuration and test method for the same 失效
标题翻译：半导体集成电路结合测试配置和测试方法相同
公开(公告)号：US07702979B2
公开(公告)日：2010-04-20
申请号：US11397899
申请日：2006-04-05
申请人： Masayuki Arai , Kazuhiko Iwasaki , Satoshi Fukumoto , Takeshi Shoda , Junichi Nishimoto
发明人： Masayuki Arai , Kazuhiko Iwasaki , Satoshi Fukumoto , Takeshi Shoda , Junichi Nishimoto
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： An object of the invention is to drastically reduce the area overhead in a semiconductor integrated circuit incorporating a test configuration that uses a partially rotational scan circuit. To achieve this, in the semiconductor integrated circuit incorporating the test configuration that comprises a combinational circuit (3) and a scan chain (2) constructed by connecting a plurality of scan flip-flops (5) in a chain, the scan chain (2) is divided into a plurality of sub scan-chains (20a to 20n) each of which has a partially rotational scan (PRS) function and a test response compaction (MISR) function. By performing a scan test in a plurality of steps while changing the combination of the sub scan-chains to be set as PRS and the sub scan-chains to be set as MISR, the test can be performed without having to provide a test response compactor separately from the scan chain, and thus the area overhead can be reduced.
摘要翻译：本发明的一个目的是大大减少包含使用部分旋转扫描电路的测试配置的半导体集成电路中的面积开销。为了实现这一点，在包括组合电路（3）和通过连接多个扫描触发器（5）构成的扫描链（2）的测试配置的半导体集成电路中，扫描链（2））被分成多个子扫描链（20a至20n），每个子扫描链具有部分旋转扫描（PRS）功能和测试响应压缩（MISR）功能。通过在将要设置为PRS的子扫描链和将被设置为MISR的副扫描链的组合改变的同时执行多个步骤中的扫描测试，可以执行测试而不必提供测试响应压缩器与扫描链分开，因此可以减少面积开销。

3. 发明授权

US07299394B2 Method and apparatus for determining optimum initial value for test pattern generator 失效
标题翻译：用于确定测试图案发生器的最佳初始值的方法和装置
公开(公告)号：US07299394B2
公开(公告)日：2007-11-20
申请号：US10400911
申请日：2003-03-28
申请人： Ken-ichi Ichino , Masayuki Arai , Satoshi Fukumoto , Kazuhiko Iwasaki , Takeshi Shoda , Masayuki Sato
发明人： Ken-ichi Ichino , Masayuki Arai , Satoshi Fukumoto , Kazuhiko Iwasaki , Takeshi Shoda , Masayuki Sato
IPC分类号： G01R31/28
CPC分类号： G06F11/261 , G01R31/3172 , G01R31/318342 , G01R31/318371
摘要： The purpose of the invention is to determine an optimum initial value to be input to a test pattern generator in order to achieve efficient testing of an integrated circuit. To achieve this purpose, a minimum test length is obtained by performing a fault simulation and a reverse-order fault simulation using an arbitrarily given initial value; the next initial value that is likely to yield a test length shorter than the minimum test length is computed and a fault simulation is performed using the thus computed initial value; and the next initial value that is likely to yield a test length shorter than that test length is computed and a fault simulation is performed using the thus computed initial value. By repeating this process, an initial value that yields the shortest test length is obtained.
摘要翻译：本发明的目的是确定要输入到测试图案发生器的最佳初始值，以便实现集成电路的有效测试。为了达到这个目的，通过使用任意给定的初始值执行故障模拟和反向故障模拟来获得最小测试长度; 计算可能产生比最小测试长度短的测试长度的下一个初始值，并且使用由此计算的初始值来执行故障模拟; 并且计算可能产生比该测试长度短的测试长度的下一个初始值，并且使用由此计算的初始值来执行故障模拟。通过重复该过程，获得产生最短测试长度的初始值。

4. 发明申请

US20110131217A1 COMPUTER PROGRAM AND COMPUTER SYSTEM FOR PRODUCING TEST FLOW 失效
标题翻译：用于生产测试流程的计算机程序和计算机系统
公开(公告)号：US20110131217A1
公开(公告)日：2011-06-02
申请号：US12958350
申请日：2010-12-01
申请人： Kazuhiko Iwasaki , Masayuki Arai , Kenichi Ichino
发明人： Kazuhiko Iwasaki , Masayuki Arai , Kenichi Ichino
IPC分类号： G06F17/30
CPC分类号： G01R31/2846
摘要： A program executed on a computer including storage, processing, output, and input units, the storage unit storing test-difficulty-calculation-elements-database, test-menu-database, and test-flow-database, for each test-menu-record, the program causing the processing unit to execute: calculating test-difficulty for each test-menu-record based on test-difficulty-calculation-formula by using at least one among pieces of information indicative of relationship with netlist, the number of package/test pins, expected operational clock frequency, process technology information, power consumption, and tester storage space; identifying all relationship between DFT scheme and priority, and causing the storage unit to store information indicative of the relationship between the DFT scheme and priority into the test-flow-database; and sorting the DFT scheme in an order of the priority based on the relationship between the DFT scheme and priority, causing the storage unit to store the DFT scheme as a test flow, and causing the output unit to output the test flow.
摘要翻译：在包括存储，处理，输出和输入单元的计算机上执行的程序，存储单元存储测试难度计算单元数据库，测试菜单数据库和测试流程数据库，记录，使得处理单元执行的程序：基于测试难度计算公式计算每个测试菜单记录的测试难度，通过使用指示与网表的关系的信息中的至少一个，包的数量 /测试引脚，预期的工作时钟频率，工艺技术信息，功耗和测试仪存储空间; 识别DFT方案和优先级之间的所有关系，并使存储单元将指示DFT方案和优先级之间的关系的信息存储到测试流数据库中; 以及根据DFT方案和优先级之间的关系按优先顺序排列DFT方案，使存储单元将DFT方案存储为测试流程，并使输出单元输出测试流程。

5. 发明授权

US08271460B2 Computer program and computer system for producing test flow 失效
标题翻译：用于生产测试流程的计算机程序和计算机系统
公开(公告)号：US08271460B2
公开(公告)日：2012-09-18
申请号：US12958350
申请日：2010-12-01
申请人： Kazuhiko Iwasaki , Masayuki Arai , Kenichi Ichino
发明人： Kazuhiko Iwasaki , Masayuki Arai , Kenichi Ichino
IPC分类号： G06F17/30
CPC分类号： G01R31/2846
摘要： A program executed on a computer including storage, processing, output, and input units, the storage unit storing test-difficulty-calculation-elements-database, test-menu-database, and test-flow-database, for each test-menu-record, the program causing the processing unit to execute: calculating test-difficulty for each test-menu-record based on test-difficulty-calculation-formula by using at least one among pieces of information indicative of relationship with netlist, the number of package/test pins, expected operational clock frequency, process technology information, power consumption, and tester storage space; identifying all relationship between DFT scheme and priority, and causing the storage unit to store information indicative of the relationship between the DFT scheme and priority into the test-flow-database; and sorting the DFT scheme in an order of the priority based on the relationship between the DFT scheme and priority, causing the storage unit to store the DFT scheme as a test flow, and causing the output unit to output the test flow.
摘要翻译：在包括存储，处理，输出和输入单元的计算机上执行的程序，存储单元存储测试难度计算单元数据库，测试菜单数据库和测试流程数据库，记录，使得处理单元执行的程序：基于测试难度计算公式计算每个测试菜单记录的测试难度，通过使用指示与网表的关系的信息中的至少一个，包的数量 /测试引脚，预期的工作时钟频率，工艺技术信息，功耗和测试仪存储空间; 识别DFT方案和优先级之间的所有关系，并使存储单元将指示DFT方案和优先级之间的关系的信息存储到测试流数据库中; 以及根据DFT方案和优先级之间的关系按优先顺序排列DFT方案，使存储单元将DFT方案存储为测试流程，并使输出单元输出测试流程。

6. 发明授权

US4926321A Method of searching a queue in response to a search instruction 失效
标题翻译：响应于搜索指令搜索队列的方法
公开(公告)号：US4926321A
公开(公告)日：1990-05-15
申请号：US089818
申请日：1987-08-27
申请人： Ken Sakamura , Kouzi Hashimoto , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki
发明人： Ken Sakamura , Kouzi Hashimoto , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki
IPC分类号： G06F9/46 , G06F9/30 , G06F9/312 , G06F17/30
CPC分类号： G06F9/30043 , G06F17/30958 , Y10S707/99933
摘要： A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing the instruction based on an output from the decoder is performed in response to a search instruction which identifies a desired data storage area from a plurality of data storage areas in the memory which includes an array data structure.
摘要翻译：一种用于搜索数据处理装置的存储器的方法，该数据处理装置包括用于解码指令内容的解码器和用于基于来自解码器的输出执行该指令的执行单元，该方法响应于识别期望数据存储器的搜索指令包括阵列数据结构的存储器中的多个数据存储区域。

7. 发明授权

US4716522A Microcomputer system with buffer in peripheral storage control 失效
标题翻译：微机系统具有缓冲区外设存储控制
公开(公告)号：US4716522A
公开(公告)日：1987-12-29
申请号：US473861
申请日：1983-03-10
申请人： Tsuneo Funabashi , Kazuhiko Iwasaki , Hideo Nakamura
发明人： Tsuneo Funabashi , Kazuhiko Iwasaki , Hideo Nakamura
IPC分类号： G06F3/06 , G06F13/00 , G06F13/28
CPC分类号： G06F3/0601 , G06F13/28 , G06F2003/0691
摘要： A microcomputer system has a peripheral storage control equipped with both a circuit which is responsive to a transfer command received from an MPU to set in a counter a transfer start address, which is designated subsequent to that command. The counter to supply an address for a buffer to control transfer of data from the output of the buffer to a common bus connected between the MPU and a RAM. A circuit is provided for controlling the aforementioned counter to count up in response to a transfer acknowledge signal which is subsequently received from a direct memory access control. In order that the data in the buffer may not be transferred to the RAM but may be rewritten, the peripheral storage control is further equipped with both a circuit for setting a rewrite address also received from the MPU in the counter, which is operative to identify the address of the selected buffer, in association with a rewrite command received from the MPU, and a circuit is also provided for applying the rewrite signal to the buffer each time the rewrite data is received after the setting operation from the MPU.
摘要翻译：微型计算机系统具有外围存储控制，该外围存储控制装置具有响应于从MPU接收到的传送命令的电路，在计数器中设置在该命令之后指定的传送起始地址。该计数器为缓冲器提供地址，以控制从缓冲器的输出到连接在MPU和RAM之间的公共总线的数据传输。提供电路，用于响应于随后从直接存储器访问控制接收的传送确认信号来控制上述计数器进行计数。为了缓冲器中的数据可能不被传送到RAM但是可以被重写，外围存储控制还配备有用于设置也从计数器中的MPU接收的重写地址的电路，其可操作地识别还提供与从MPU接收的重写命令相关联的所选择的缓冲器的地址和电路，用于在每次在来自MPU的设置操作之后接收到重写数据时，将重写信号施加到缓冲器。

8. 发明授权

US07091149B2 Electrode for fuel cell, method of manufacturing same, and fuel cell with such electrode 有权
公开(公告)号：US07091149B2
公开(公告)日：2006-08-15
申请号：US10187552
申请日：2002-07-01
申请人： Kazuhiko Iwasaki , Tsugio Ohba , Takeshi Miyama , Minako Onodera
发明人： Kazuhiko Iwasaki , Tsugio Ohba , Takeshi Miyama , Minako Onodera
IPC分类号： B01J21/18 , B05D5/12 , B29C65/00 , B32B37/00
CPC分类号： H01M4/8807 , H01M4/8605 , H01M4/8817 , H01M4/8882 , H01M4/8896 , H01M4/96 , H01M2300/0005 , H01M2300/0008 , H01M2300/0011
摘要： A fuel cell provides a high output at a high current density. The fuel cell has an anode electrode and a cathode electrode comprising a gas diffusion layer, a water-repellent layer disposed on the gas diffusion layer and containing a carbon material and polytetrafluoroethylene, and an electrode catalyst layer disposed on the water-repellent layer and containing a carbon material carrying a catalyst. The electrode catalyst layer has maximum and minimum thicknesses that differ from each other by less than 30 μm. The electrode catalyst layer has cracks whose area is less than 10% of a total area of the electrode catalyst layer.

9. 发明申请

US20050170222A1 Full cell electrocatalyst of pt-ni-mn/fe 审中-公开
标题翻译： pt-ni-mn / fe的全细胞电催化剂
公开(公告)号：US20050170222A1
公开(公告)日：2005-08-04
申请号：US10505622
申请日：2003-02-27
申请人： Peter Strasser , Alexander Gorer , Martin Devenney , Ting He , Hiroyuki Oyanagi , Qun Fan , Konstantinos Chondroudis , Daniel Giaquinta , Kenta Urata , Kazuhiko Iwasaki , Hiroichi Fukuda
发明人： Peter Strasser , Alexander Gorer , Martin Devenney , Ting He , Hiroyuki Oyanagi , Qun Fan , Konstantinos Chondroudis , Daniel Giaquinta , Kenta Urata , Kazuhiko Iwasaki , Hiroichi Fukuda
IPC分类号： B01J21/18 , B01J23/40 , B01J23/656 , B01J23/89 , C22C5/04 , H01M4/86 , H01M4/88 , H01M4/92 , H01M8/06 , H01M8/10 , H01M8/22
CPC分类号： H01M8/1004 , B01J21/18 , B01J23/892 , B01J23/8986 , C22C5/04 , H01M4/8803 , H01M4/881 , H01M4/921 , H01M4/925 , H01M4/926 , H01M4/928 , H01M8/1009 , H01M8/1011 , H01M8/22 , Y02E60/523
摘要： An improved metal alloy composition for a fuel cell catalyst containing platinum, nickel, and manganese or iron.
摘要翻译：一种用于包含铂，镍和锰或铁的燃料电池催化剂的改进的金属合金组合物。

10. 发明授权

US5170474A Method of searching a queue in response to a search instruction 失效
标题翻译：响应于搜索指令搜索队列的方法
公开(公告)号：US5170474A
公开(公告)日：1992-12-08
申请号：US755742
申请日：1991-09-24
申请人： Ken Sakamura , Kouzi Hashimoto , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki
发明人： Ken Sakamura , Kouzi Hashimoto , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki
IPC分类号： G06F9/312 , G06F17/30
CPC分类号： G06F9/30043 , G06F17/30958 , Y10S707/99936
摘要： A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing is performed in response to an instruction based on an output from the decoder, the search instruction which identifies a desired data storage area from a plurality of data storage areas in the memory which includes an array data structure.
摘要翻译：响应于来自解码器的输出的指令，执行包括用于解码指令的内容的解码器和用于执行的执行单元的数据处理装置的存储器的方法，所述搜索指令识别期望的数据从存储器中的包括阵列数据结构的多个数据存储区域的存储区域。

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