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1. 发明授权

US07259058B2 Fabricating method of semiconductor integrated circuits 有权
标题翻译：半导体集成电路的制造方法
公开(公告)号：US07259058B2
公开(公告)日：2007-08-21
申请号：US10020314
申请日：2001-12-18
申请人： Yasuhiro Shimamoto , Masahiko Hiratani , Yuichi Matsui , Satoshi Yamamoto , Toshihide Nabatame , Toshio Ando , Hiroshi Sakuma , Shinpei Iijima
发明人： Yasuhiro Shimamoto , Masahiko Hiratani , Yuichi Matsui , Satoshi Yamamoto , Toshihide Nabatame , Toshio Ando , Hiroshi Sakuma , Shinpei Iijima
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , C23C16/18 , H01L21/28556 , H01L21/28568 , H01L28/55 , H01L28/91
摘要： A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.
摘要翻译：通过化学气相沉积法形成氧气污染少，热稳定性高的钌电极。在使用有机钌化合物作为前体的化学气相沉积方法中，氧化气体的引入限于当前体供应时，并且允许反应在低氧分压下发生。因此，可以形成氧含量低的钌膜。此外，在形成钌膜之后，进行不低于形成温度的退火，由此形成热稳定性高的钌膜。

2. 发明授权

US06992022B2 Fabrication method for semiconductor integrated devices 失效
公开(公告)号：US06992022B2
公开(公告)日：2006-01-31
申请号：US10795430
申请日：2004-03-09
申请人： Yasuhiro Shimamoto , Masahiko Hiratani , Yuichi Matsui , Toshihide Nabatame
发明人： Yasuhiro Shimamoto , Masahiko Hiratani , Yuichi Matsui , Toshihide Nabatame
IPC分类号： H01L21/31
CPC分类号： H01L28/60 , C23C16/18 , C23C16/409 , H01L21/28556 , H01L21/31604 , H01L27/10814 , H01L28/55
摘要： A process for forming the lower and upper electrodes of a high dielectric constant capacitor in a semiconductor device from an organoruthenium compound by chemical vapor deposition. This chemical vapor deposition technique employs an organoruthenium compound, an oxidizing gas, and a gas (such as argon) which is hardly adsorbed to the ruthenium surface or a gas (such as ethylene) which is readily adsorbed to the ruthenium surface. This process efficiently forms a ruthenium film with good conformality in a semiconductor device.

3. 发明授权

US06989304B1 Method for manufacturing a ruthenium film for a semiconductor device 失效
标题翻译：半导体装置用钌膜的制造方法
公开(公告)号：US06989304B1
公开(公告)日：2006-01-24
申请号：US10297811
申请日：2000-08-11
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Toshihide Nabatame
IPC分类号： H01L21/8242
CPC分类号： C23C14/046 , C23C14/165 , C23C16/18 , H01L21/7687 , H01L27/10814 , H01L27/10852 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/91
摘要： In the method of manufacturing a semiconductor device according to this invention, when an interlayer insulating film is fabricated such that an opening is cylindrical and low-pressure and long-throw sputtering is used for forming a lower ruthenium electrode, a ruthenium film can be deposited on the side wall of a deep hole. Further, after removing the ruthenium film deposited on the upper surface of the interlayer insulating film, a dielectric material comprising, for example, a tantalum pentoxide film is deposited. Successively, an upper ruthenium electrode is deposited using, for example, Ru(EtCp)2 as a starting material and by chemical vapor deposition of conveying the starting material by bubbling. The upper ruthenium electrode can be formed with good coverage by using conditions that the deposition rate of the ruthenium film depends on the formation temperature (reaction controlling condition). This invention can provide a fine concave type capacitor having a ruthenium electrode.
摘要翻译：在根据本发明的半导体器件的制造方法中，当制造使得开口为圆柱形的层间绝缘膜并且使用低压和长距离溅射来形成下部钌电极时，可以沉积钌膜在一个深孔的侧壁上。此外，在除去沉积在层间绝缘膜的上表面上的钌膜之后，沉积包括例如五氧化二钽膜的电介质材料。接着，使用例如Ru（EtCp）2 N 2作为起始材料并通过化学气相沉积，通过鼓泡输送起始材料来沉积上钌电极。通过使用钌膜的沉积速率取决于形成温度（反应控制条件）的条件，可以形成具有良好覆盖度的上钌电极。本发明可以提供一种具有钌电极的细凹型电容器。

4. 发明授权

US06521494B2 Method of manufacturing semiconductor devices utilizing underlayer-dependency of deposition of capacitor electrode film, and semiconductor device 有权
公开(公告)号：US06521494B2
公开(公告)日：2003-02-18
申请号：US10211569
申请日：2002-08-05
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/28562 , H01L27/10814
摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.

5. 发明授权

US06503791B2 Method of manufacturing semiconductor devices utilizing underlayer-dependency of deposition of capacitor electrode film, and semiconductor device 有权
标题翻译：利用电容电极膜的沉积的下层依赖性制造半导体器件的方法和半导体器件
公开(公告)号：US06503791B2
公开(公告)日：2003-01-07
申请号：US09767706
申请日：2001-01-24
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/28562 , H01L27/10814
摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film.
摘要翻译：在包括多个存储单元的半导体器件中，在形成有多个孔的层间绝缘膜上形成防沉积膜，或者在层间绝缘膜和内表面上选择性地形成晶种膜，孔的底面。在发生底层依赖性的条件下，通过化学气相沉积在沉积防止膜上或通过利用种子膜在层间绝缘膜上沉积Ru，Ir或Pt的膜。因此，根据防沉积膜或种子膜的图案形成下部电极。

6. 发明授权

US06743739B2 Fabrication method for semiconductor integrated devices 失效
公开(公告)号：US06743739B2
公开(公告)日：2004-06-01
申请号：US10101600
申请日：2002-03-21
申请人： Yasuhiro Shimamoto , Masahiko Hiratani , Yuichi Matsui , Toshihide Nabatame
发明人： Yasuhiro Shimamoto , Masahiko Hiratani , Yuichi Matsui , Toshihide Nabatame
IPC分类号： H01L2131
CPC分类号： H01L28/60 , C23C16/18 , C23C16/409 , H01L21/28556 , H01L21/31604 , H01L27/10814 , H01L28/55
摘要： A process for forming the lower and upper electrodes of a high dielectric constant capacitor in a semiconductor device from an organoruthenium compound by chemical vapor deposition. This chemical vapor deposition technique employs an organoruthenium compound, an oxidizing gas, and a gas (such as argon) which is hardly adsorbed to the ruthenium surface or a gas (such as ethylene) which is readily adsorbed to the ruthenium surface. This process efficiently forms a ruthenium film with good conformality in a semiconductor device.

7. 发明授权

US06555429B2 Method of manufacturing semiconductor devices utilizing underlayer-dependency of deposition of capacitor electrode film, and semiconductor device 有权
公开(公告)号：US06555429B2
公开(公告)日：2003-04-29
申请号：US09810627
申请日：2001-03-19
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/28562 , H01L27/10814
摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.

8. 发明授权

US06483143B2 Semiconductor device having a capacitor structure including a self-alignment deposition preventing film 有权
标题翻译：具有包括自对准防沉积膜的电容器结构的半导体器件
公开(公告)号：US06483143B2
公开(公告)日：2002-11-19
申请号：US09810401
申请日：2001-03-19
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
IPC分类号： H01L27108
CPC分类号： H01L28/60 , H01L21/28562 , H01L27/10814
摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.
摘要翻译：在包括多个存储单元的半导体器件中，在形成有多个孔的层间绝缘膜上形成防沉积膜，或者在层间绝缘膜和内表面上选择性地形成晶种膜，孔的底面。在发生底层依赖性的条件下，通过化学气相沉积在沉积防止膜上或通过利用种子膜在层间绝缘膜上沉积Ru，Ir或Pt的膜。因此，根据防沉积膜或种子膜的图案形成下部电极。在预定温度下在下电极和防沉积膜上形成电介质膜。即使暴露在用于形成电介质膜的预定温度下，下电极的材料也不会导通。上电极进一步形成在电介质膜上。上下电极和氧化物介质膜一起构成存储单元的电容器。

9. 发明授权

US06534375B2 METHOD OF FORMING A CAPACITOR IN A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING A METAL SILICON NITRIDE LAYER TO PROTECT AN UNDERLYING METAL SILICIDE LAYER FROM OXIDATION DURING SUBSEQUENT PROCESSING STEPS 有权
标题翻译：在半导体集成电路器件中形成电容器的方法使用金属硅化物层在后续处理步骤中从氧化物中保护金属硅酸盐层
公开(公告)号：US06534375B2
公开(公告)日：2003-03-18
申请号：US09923406
申请日：2001-08-08
申请人： Shinpei Iijima , Yuzuru Ohji , Masato Kunitomo , Masahiko Hiratani , Yuichi Matsui , Hiroyuki Ohta , Yukihiro Kumagai
发明人： Shinpei Iijima , Yuzuru Ohji , Masato Kunitomo , Masahiko Hiratani , Yuichi Matsui , Hiroyuki Ohta , Yukihiro Kumagai
IPC分类号： H01L21285
CPC分类号： H01L21/02183 , H01L21/02271 , H01L21/02337 , H01L21/02356 , H01L21/31637 , H01L27/10814 , H01L27/10855 , H01L28/60 , H01L28/91
摘要： A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.
摘要翻译：形成在DRAM的电容元件的下部电极上形成的电介质膜的氧气氛中的氧气的缺点是氧气渗透下部电极氧化阻挡层以形成高电阻和低介电常数的氧化物层。在形成在信息容纳电容元件C的下部电极下方的通孔中的插塞表面上形成Ru Ru硅化物层，并且在Ru硅化物层的表面上进一步形成Ru氮化硅层。在下电极上形成电介质膜的步骤中进行的氧气氛中进行高温热处理时，将Ru氮化硅层牺牲性氧化为Ru氮氧化硅，以防止Ru化硅化物层的氧化进行。

10. 发明授权

US06664157B2 Semiconductor integrated circuit device and the method of producing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06664157B2
公开(公告)日：2003-12-16
申请号：US09775547
申请日：2001-02-05
申请人： Shinpei Iijima , Yoshitaka Nakamura , Masahiko Hiratani , Yuichi Matsui , Naruhiko Nakanishi
发明人： Shinpei Iijima , Yoshitaka Nakamura , Masahiko Hiratani , Yuichi Matsui , Naruhiko Nakanishi
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10888 , H01L28/91
摘要： Plug electrodes of silicon are formed so as to be buried in through holes in a first insulating film, the plug electrodes being electrically connected to the source and drain regions of a MISFET on the main surface of a semiconductor substrate. Then, a second insulating film is deposited thereon and holes are formed therein such that the plug electrodes of silicon are exposed. A barrier film is formed on the surfaces of the silicon plugs, and in the holes a dielectric is formed to form lower electrodes of the capacitor elements and an upper electrode therefor.
摘要翻译：形成硅的插入电极以埋在第一绝缘膜的通孔中，插塞电极与半导体衬底的主表面上的MISFET的源极和漏极区域电连接。然后，在其上沉积第二绝缘膜，并在其中形成孔，使得硅的插塞电极露出。在硅插头的表面上形成阻挡膜，并且在孔中形成电介质以形成电容器元件的下电极和用于其的上电极。

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