专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07259058B2 Fabricating method of semiconductor integrated circuits 有权
标题翻译：半导体集成电路的制造方法
公开(公告)号：US07259058B2
公开(公告)日：2007-08-21
申请号：US10020314
申请日：2001-12-18
申请人： Yasuhiro Shimamoto , Masahiko Hiratani , Yuichi Matsui , Satoshi Yamamoto , Toshihide Nabatame , Toshio Ando , Hiroshi Sakuma , Shinpei Iijima
发明人： Yasuhiro Shimamoto , Masahiko Hiratani , Yuichi Matsui , Satoshi Yamamoto , Toshihide Nabatame , Toshio Ando , Hiroshi Sakuma , Shinpei Iijima
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , C23C16/18 , H01L21/28556 , H01L21/28568 , H01L28/55 , H01L28/91
摘要： A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.
摘要翻译：通过化学气相沉积法形成氧气污染少，热稳定性高的钌电极。在使用有机钌化合物作为前体的化学气相沉积方法中，氧化气体的引入限于当前体供应时，并且允许反应在低氧分压下发生。因此，可以形成氧含量低的钌膜。此外，在形成钌膜之后，进行不低于形成温度的退火，由此形成热稳定性高的钌膜。

2. 发明授权

US07074669B2 Semiconductor integrated circuit device with capacitor of crown structure and method of manufacturing the same 失效
公开(公告)号：US07074669B2
公开(公告)日：2006-07-11
申请号：US10443572
申请日：2003-05-22
申请人： Shinpei Iijima , Hiroshi Sakuma
发明人： Shinpei Iijima , Hiroshi Sakuma
IPC分类号： H01L21/8242
CPC分类号： H01L28/65 , H01L21/31604 , H01L27/10814 , H01L27/10855 , H01L27/10882 , H01L27/10894 , H01L28/75 , H01L28/90
摘要： A semiconductor integrated circuit device includes a plurality of capacitor elements, which are separated from each other by a first insulating film on a plane. Each of the plurality of capacitor elements has a lower electrode, a dielectric film, and an upper electrode, and the lower electrode has a crown structure. At least one of the lower electrode and the upper electrode has a laminate structure composed of a plurality of conductive films. An outermost film of the laminate structure on a side of the dielectric film is a ruthenium film, and a portion of the laminate structure other than the outermost film has higher selective growth than the first insulating film with respect to the ruthenium film. Here, the first insulating film is desirably a tantalum oxide film.

3. 发明授权

US06724034B2 Semiconductor integrated circuit device and manufacturing method which avoids oxidation of silicon plug during thermal treatment of capacitor insulating film 失效
标题翻译：半导体集成电路器件及其制造方法，可避免电容器绝缘膜热处理过程中硅插头的氧化
公开(公告)号：US06724034B2
公开(公告)日：2004-04-20
申请号：US10230107
申请日：2002-08-29
申请人： Shinpei Iijima , Hiroshi Sakuma
发明人： Shinpei Iijima , Hiroshi Sakuma
IPC分类号： H01L27108
CPC分类号： H01L28/60 , H01L21/28518 , H01L27/10814 , H01L28/55 , H01L28/91
摘要： In a semiconductor integrated circuit device, a polycrystalline silicon film is formed along an inner wall of a trench in which a capacitor is to be formed, and the polycrystalline silicon film and a lower electrode is contacted to each other on the entire inner wall of the trench. Oxygen permeated into the lower electrode during a thermal treatment of a tantalum oxide film is consumed at an interface between the polycrystalline silicon film and the lower electrode. Thus, oxygen does not reach the surface of a silicon plug below the lower electrode that would cause oxidation on the surface of the silicon plug and form a high-resistance oxide layer when a dielectric film formed on a lower electrode of a capacitor of a DRAM is subjected to a thermal treatment in an oxygen atmosphere.
摘要翻译：在半导体集成电路器件中，沿着要形成电容器的沟槽的内壁形成多晶硅膜，并且多晶硅膜和下电极在其整个内壁上彼此接触沟。在氧化钽膜的热处理期间，氧气渗入下电极在多晶硅膜和下电极之间的界面消耗。因此，当形成在DRAM的电容器的下电极上的电介质膜时，氧不会到达下电极下方的硅插塞的表面，这将导致硅插塞的表面上的氧化并形成高电阻的氧化物层在氧气氛中进行热处理。

4. 发明授权

US07183170B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07183170B2
公开(公告)日：2007-02-27
申请号：US10998804
申请日：2004-11-30
申请人： Yoshitaka Nakamura , Tsuyoshi Kawagoe , Hiroshi Sakuma , Isamu Asano , Keiji Kuroki , Hidekazu Goto , Shinpei Iijima
发明人： Yoshitaka Nakamura , Tsuyoshi Kawagoe , Hiroshi Sakuma , Isamu Asano , Keiji Kuroki , Hidekazu Goto , Shinpei Iijima
IPC分类号： H01L21/20
CPC分类号： H01L28/65 , H01L21/32136 , H01L27/10814 , H01L27/10852 , H01L27/10882 , H01L28/91
摘要： After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.
摘要翻译：在形成上部电极保护膜使得其与上部电极的钌膜牢固接触而不损坏钌膜之后，蚀刻上部电极，由此获得漏电流不增加的MIM电容器以使上电极的钌膜氧化。

5. 发明申请

US20050118762A1 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20050118762A1
公开(公告)日：2005-06-02
申请号：US10998804
申请日：2004-11-30
申请人： Yoshitaka Nakamura , Tsuyoshi Kawagoe , Hiroshi Sakuma , Isamu Asano , Keiji Kuroki , Hidekazu Goto , Shinpei Iijima
发明人： Yoshitaka Nakamura , Tsuyoshi Kawagoe , Hiroshi Sakuma , Isamu Asano , Keiji Kuroki , Hidekazu Goto , Shinpei Iijima
IPC分类号： C23C16/40 , H01L21/02 , H01L21/316 , H01L21/3213 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/65 , H01L21/32136 , H01L27/10814 , H01L27/10852 , H01L27/10882 , H01L28/91
摘要： After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.
摘要翻译：在形成上部电极保护膜使得其与上部电极的钌膜牢固接触而不损坏钌膜之后，蚀刻上部电极，由此获得漏电流不增加的MIM电容器以使上电极的钌膜氧化。

6. 发明授权

US06723612B2 Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06723612B2
公开(公告)日：2004-04-20
申请号：US10353953
申请日：2003-01-30
申请人： Shinpei Iijima , Hiroshi Sakuma
发明人： Shinpei Iijima , Hiroshi Sakuma
IPC分类号： H01L2120
CPC分类号： H01L28/60 , H01L21/28518 , H01L27/10814 , H01L28/55 , H01L28/91
摘要： In a semiconductor integrated circuit device, a polycrystalline silicon film is formed along an inner wall of a trench in which a capacitor is to be formed, and the polycrystalline silicon film and a lower electrode are contacted to each other on the entire inner wall of the trench. Oxygen permeated into the lower electrode during a thermal treatment of a tantalum oxide film is consumed at an interface between the polycrystalline silicon film and the lower electrode. Thus, oxygen does not reach the surface of a silicon plug below the lower electrode that would cause oxidation on the surface of the silicon plug and form a high-resistance oxide layer when a dielectric film formed on a lower electrode of a capacitor of a DRAM is subjected to a thermal treatment in an oxygen atmosphere.
摘要翻译：在半导体集成电路器件中，沿着要形成电容器的沟槽的内壁形成多晶硅膜，并且多晶硅膜和下电极在其整个内壁上彼此接触沟。在氧化钽膜的热处理期间，氧气渗入下电极在多晶硅膜和下电极之间的界面消耗。因此，当形成在DRAM的电容器的下电极上的电介质膜时，氧不会到达下电极下方的硅插塞的表面，这将导致硅插塞的表面上的氧化并形成高电阻的氧化物层在氧气氛中进行热处理。

7. 发明授权

US07119443B2 Semiconductor integrated circuit device having a conductive film which contains metal atoms bondable to a halogen element 有权
标题翻译：具有导电膜的半导体集成电路器件，其包含可与卤素元件键合的金属原子
公开(公告)号：US07119443B2
公开(公告)日：2006-10-10
申请号：US10959634
申请日：2004-10-07
申请人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
发明人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/31 , H01L21/469
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
摘要翻译：根据以下步骤形成半导体器件。通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀仅留下通孔66的内部并形成插头73。然后，通过溅射法将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，然后，将Ti膜76，Al合金膜75，并且将TiN膜74图案化以形成第二层布线77和78。

8. 发明授权

US06853081B2 Method for fabricating semiconductor integrated circuit 有权
标题翻译：制造半导体集成电路的方法
公开(公告)号：US06853081B2
公开(公告)日：2005-02-08
申请号：US10453611
申请日：2003-06-04
申请人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
发明人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
IPC分类号： H01L21/8242 , H01L23/522 , H01L23/48 , H01L21/44 , H01L21/4763 , H01L23/52 , H01L29/40
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
摘要翻译：根据以下步骤形成半导体器件。通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀仅留下通孔66的内部并形成插头73.然后，将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，通过溅射法，然后对Ti膜76，Al合金膜75和TiN膜74进行图案化以形成第二层布线77和78。

9. 发明授权

US06605530B2 Method for fabricating semiconductor integrated circuit 有权
公开(公告)号：US06605530B2
公开(公告)日：2003-08-12
申请号：US10287616
申请日：2002-11-05
申请人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
发明人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
IPC分类号： H01L214763
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

10. 发明授权

US07845231B2 Shear measuring method and its device 有权
标题翻译：剪切测量方法及其装置
公开(公告)号：US07845231B2
公开(公告)日：2010-12-07
申请号：US12088046
申请日：2006-09-27
申请人： Kazue Kurihara , Hiroshi Sakuma , Masashi Mizukami
发明人： Kazue Kurihara , Hiroshi Sakuma , Masashi Mizukami
IPC分类号： G01H13/00 , G01N3/24
CPC分类号： G01N19/04 , G01N2203/0025
摘要： A resonance shear measuring method capable of simple and rapid measurement by obtaining a resonance shear curve through Fourier transformation of a damping curve of an oscillation on one side surface of a sample during measurement of shear response from the sample is provided. The method is to measure shear response of the sample sandwiched between the solid surfaces of a resonance shear measurement unit along with a change in film thickness by applying an input signal Uin to a horizontal driving section of the shear resonance measurement unit, by detecting an oscillation on one side surface of the sample sandwiched between solid surfaces of the resonance shear measurement unit as an output signal Uout by means of a displacement gauge, and by applying the output signal Uout along with the input signal Uin to a resonance shear signal analyzer, wherein a damping curve of the oscillation on one side surface of the sample is Fourier transformed by a Fourier transformation section (5B) to obtain a resonance shear curve. Also provided is a twin-path type apparatus for shear stress measurement capable of precise measurement of shear stress by using a twin-path method by which a distance between opaque substrates can be measured.
摘要翻译：提供一种共振剪切测量方法，其能够通过在从样品的剪切响应测量期间在样品的一个侧表面上的振荡的阻尼曲线通过傅里叶变换获得共振剪切曲线来简单且快速地测量。该方法是通过将输入信号Uin施加到剪切共振测量单元的水平驱动部分，通过检测振荡来测量夹在共振剪切测量单元的固体表面之间的样品的剪切响应以及膜厚度的变化在夹持在谐振剪切测量单元的固体表面之间的样品的一个侧表面上，通过位移计将输出信号Uout与输入信号Uin一起施加到谐振剪切信号分析仪，其中，通过傅立叶变换部（5B）对样品的一个侧面的振动的阻尼曲线进行傅里叶变换，得到共振剪切曲线。还提供了一种用于剪切应力测量的双路型装置，其能够通过使用可以测量不透明基板之间的距离的双路径方法来精确测量剪切应力。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式