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1. 发明授权

US06144412A Method and circuit for signal processing of format conversion of picture signal 失效
标题翻译：图像信号格式转换的信号处理方法和电路
公开(公告)号：US06144412A
公开(公告)日：2000-11-07
申请号：US950666
申请日：1997-10-15
申请人： Yasuhiro Hirano , Kazuo Ishikura , Masato Sugiyama , Mitsuo Nakajima , Shoji Kimura , Toshiyuki Kurita , Tsuguo Itagaki , Haruki Takata
发明人： Yasuhiro Hirano , Kazuo Ishikura , Masato Sugiyama , Mitsuo Nakajima , Shoji Kimura , Toshiyuki Kurita , Tsuguo Itagaki , Haruki Takata
IPC分类号： H04N5/46 , G06T3/40 , G09G5/00 , H04N3/223 , H04N7/01 , H04N11/20
CPC分类号： G06T3/4007 , H04N7/012 , H04N7/0122
摘要： In order to carry out format conversion or scaling processing of picture signal by a memory having a small capacity, picture signals of interlace scanning are converted into picture signals of progressive scanning by interpolation by using an IP convertor 1 and a multiple scan convertor 3, a scaling processing of expansion and compression in the horizontal direction is firstly performed by using a horizontal scaling unit 5, processing of expansion, compression, frame rate conversion, synchronization and the like are secondly performed by using a vertical scaling unit 6 and commonly using memories used in scaling processing in the vertical direction and finally, color space conversion or inverse gamma processing is performed by using a picture quality improving unit 8 thereby converting the picture signals into picture signals S6 having a predetermined format.
摘要翻译：为了通过具有小容量的存储器执行图像信号的格式转换或缩放处理，隔行扫描的图像信号通过使用IP转换器1和多扫描转换器3进行插值而被转换为逐行扫描的图像信号，首先通过使用水平缩放单元5执行水平方向上的扩展和压缩的缩放处理，通过使用垂直缩放单元6并且通常使用所使用的存储器来再次执行扩展，压缩，帧速率转换，同步等的处理在垂直方向的缩放处理中，最后，通过使用图像质量改善单元8执行颜色空间转换或反伽马处理，从而将图像信号转换为具有预定格式的图像信号S6。

2. 发明授权

US4821112A Detection circuit for detecting standard television signals and nonstandard television signals 失效
标题翻译：用于检测标准电视信号和非标准电视信号的检测电路
公开(公告)号：US4821112A
公开(公告)日：1989-04-11
申请号：US63477
申请日：1987-06-18
申请人： Toshiyuki Sakamoto , Ikuya Arai , Toshiyuki Kurita , Toshinori Murata , Isao Nakagawa , Masahiko Achiha , Kazuo Ishikura
发明人： Toshiyuki Sakamoto , Ikuya Arai , Toshiyuki Kurita , Toshinori Murata , Isao Nakagawa , Masahiko Achiha , Kazuo Ishikura
IPC分类号： H04N9/804 , H04N9/64 , H04N9/78 , H04N9/808 , H04N9/87 , H04N9/89 , H04N9/44
CPC分类号： H04N9/641
摘要： There is provided a detection circuit for TV receiver which includes a frame comb filter and a field comb filter and which generates a luminance signal or a chrominance signal by effecting addition or subtraction upon video signals of two frames adjoining each other included in the received TV signal. This detection circuit includes a synchronization separation circuit, an APC circuit, a frequency division circuit connected to the APC circuit, and a comparator circuit connected to the frequency division circuit. The frequency of the chrominance subcarrier signal is demultiplied by the frequency division circuit. The phase of the chrominance subcarrier signal thus frequency-divided is compared with the phase of the synchronizing signal separated by the synchronizing separation circuit. It is thus judged whether the received TV signal is a standard TV signal or a nonstandard TV signal.
摘要翻译：提供了一种用于TV接收机的检测电路，其包括帧梳状滤波器和场梳状滤波器，并且通过对包含在所接收的TV信号中的彼此相邻的两个帧的视频信号进行加法或减法而产生亮度信号或色度信号。该检测电路包括同步分离电路，APC电路，连接到APC电路的分频电路，以及连接到分频电路的比较电路。色差副载波信号的频率由分频电路分频。将这样分频的色度副载波信号的相位与由同步分离电路分离的同步信号的相位进行比较。因此判断所接收的TV信号是标准TV信号还是非标准TV信号。

3. 发明申请

US20090102972A1 Display Apparatus 有权
标题翻译：显示装置
公开(公告)号：US20090102972A1
公开(公告)日：2009-04-23
申请号：US12252422
申请日：2008-10-16
申请人： Toshiyuki Kurita , Hitoaki Owashi
发明人： Toshiyuki Kurita , Hitoaki Owashi
IPC分类号： H04N3/27
CPC分类号： G09G5/006 , G06F3/0481 , G06F3/0482 , G06T1/0007 , G09G5/005 , G09G2340/02 , G09G2354/00 , G09G2360/02 , G09G2370/12 , H04N1/00129 , H04N1/00137 , H04N1/00164 , H04N1/00172 , H04N1/00177 , H04N1/00198 , H04N1/00307 , H04N1/00347 , H04N1/00442 , H04N1/00453 , H04N1/00458 , H04N1/00461 , H04N21/4122 , H04N21/4223 , H04N21/43632 , H04N21/43635 , H04N21/43637 , H04N21/43853 , H04N21/440263 , H04N21/4438 , H04N21/4627 , H04N21/6112 , H04N21/6131 , H04N2201/0049 , H04N2201/0055 , H04N2201/0084 , H04N2201/0086 , H04N2201/0087 , H04N2201/0089
摘要： A display apparatus transmits a picture acquisition request for getting picture information to an external image apparatus connected through a predetermined interface to the display apparatus from the external image apparatus at predetermined intervals and gets a plurality of pieces of picture information from the external image apparatus to be displayed. The plurality of pictures may be switched at predetermined intervals, for example, to be displayed, so that the plurality of pictures may be displayed in a so-called slide show manner. A plurality of pictures for thumbnail may be produced from the plurality of pieces of picture information and be arranged together to be displayed in one picture screen of a display device.
摘要翻译：显示装置以预定间隔从外部图像装置向通过预定接口连接的外部图像装置发送用于获得图像信息的图像获取请求，并从外部图像装置获取多条图像信息，显示。可以以预定间隔切换多个图像，例如显示，使得可以以所谓的幻灯片显示方式显示多个图像。可以从多张图像信息生成用于缩略图的多个图像，并将其布置在一起显示在显示装置的一个图像画面中。

4. 发明申请

US20070085776A1 Display apparatus and display panel 审中-公开
标题翻译：显示设备和显示面板
公开(公告)号：US20070085776A1
公开(公告)日：2007-04-19
申请号：US11523081
申请日：2006-09-19
申请人： Mikio Shiraishi , Eiji Miwa , Toshiyuki Kurita , Katsumi Ashizawa
发明人： Mikio Shiraishi , Eiji Miwa , Toshiyuki Kurita , Katsumi Ashizawa
IPC分类号： G09G3/22
CPC分类号： G09G3/22 , G09G2300/06 , G09G2310/0267 , G09G2310/0275 , G09G2310/06
摘要： An electron emission type display apparatus has on a flat plane a matrix layout of multiple light-emitting elements which are connected to cross-points of longitudinal and lateral common electrodes, for sequentially turning on a line of light-emitting elements connected to a common electrode. In such the device, distortion takes place in drive waveform since a low-pass filter (LPF) is formed by a combination of the wiring resistance of the common electrode and the capacitance of a light-emitting element. To avoid such waveform distortion, the width of a light-emitting element driving voltage pulse is caused to be greater than the width of a scan voltage pulse.
摘要翻译：电子发射型显示装置在平面上具有连接到纵向和横向公共电极的交叉点的多个发光元件的矩阵布局，用于顺序地接通连接到公共电极的一行发光元件。在这种装置中，由于通过公共电极的布线电阻和发光元件的电容的组合形成低通滤波器（LPF），所以在驱动波形中发生失真。为了避免这种波形失真，使得发光元件驱动电压脉冲的宽度大于扫描电压脉冲的宽度。

5. 发明授权

US09420212B2 Display apparatus and video processing apparatus 有权
标题翻译：显示装置和视频处理装置
公开(公告)号：US09420212B2
公开(公告)日：2016-08-16
申请号：US12260410
申请日：2008-10-29
申请人： Toshiyuki Kurita , Hitoaki Owashi
发明人： Toshiyuki Kurita , Hitoaki Owashi
IPC分类号： H04N5/44 , H04N21/4363 , H04L29/06 , H04N21/41 , H04N21/414 , H04N21/4367
CPC分类号： H04N21/43637 , H04L69/14 , H04N5/44 , H04N21/4122 , H04N21/41407 , H04N21/4367
摘要： While presenting on a display apparatus videos of high picture quality obtained from portable video processing apparatuses such as a camera and a cellular, it is possible to communicate with the Internet and/or a home network. A display apparatus includes a first radio communication unit capable of receiving video information by radio from an external video processing apparatus, a second radio communication unit capable of connecting by radio to a network, and a control unit for controlling assignment of connection by radio transmission for each of the first and second radio communication units. The control unit assigns connection of the first radio communication unit with higher priority and controls the assignment of the transmission rate such that the transmission rate between the first radio communication unit and the external video processing apparatus is more than that between the second radio communication unit and the network.
摘要翻译：在显示装置上呈现从诸如照相机和蜂窝的便携式视频处理装置获得的高图像质量的视频时，可以与因特网和/或家庭网络进行通信。显示装置包括能够通过无线电从外部视频处理装置接收视频信息的第一无线电通信单元，能够通过无线电连接到网络的第二无线电通信单元，以及用于通过无线电传输控制连接分配的控制单元第一和第二无线电通信单元中的每一个。控制单元以较高的优先级分配第一无线电通信单元的连接，并且控制传输速率的分配，使得第一无线电通信单元和外部视频处理设备之间的传输速率大于第二无线电通信单元和网络。

6. 发明授权

US08446528B2 Display apparatus 有权
公开(公告)号：US08446528B2
公开(公告)日：2013-05-21
申请号：US12252422
申请日：2008-10-16
申请人： Toshiyuki Kurita , Hitoaki Owashi
发明人： Toshiyuki Kurita , Hitoaki Owashi
IPC分类号： H04N5/44
CPC分类号： G09G5/006 , G06F3/0481 , G06F3/0482 , G06T1/0007 , G09G5/005 , G09G2340/02 , G09G2354/00 , G09G2360/02 , G09G2370/12 , H04N1/00129 , H04N1/00137 , H04N1/00164 , H04N1/00172 , H04N1/00177 , H04N1/00198 , H04N1/00307 , H04N1/00347 , H04N1/00442 , H04N1/00453 , H04N1/00458 , H04N1/00461 , H04N21/4122 , H04N21/4223 , H04N21/43632 , H04N21/43635 , H04N21/43637 , H04N21/43853 , H04N21/440263 , H04N21/4438 , H04N21/4627 , H04N21/6112 , H04N21/6131 , H04N2201/0049 , H04N2201/0055 , H04N2201/0084 , H04N2201/0086 , H04N2201/0087 , H04N2201/0089
摘要： A display apparatus transmits a picture acquisition request for getting picture information to an external image apparatus connected through a predetermined interface to the display apparatus from the external image apparatus at predetermined intervals and gets a plurality of pieces of picture information from the external image apparatus to be displayed. The plurality of pictures may be switched at predetermined intervals, for example, to be displayed, so that the plurality of pictures may be displayed in a so-called slide show manner. A plurality of pictures for thumbnail may be produced from the plurality of pieces of picture information and be arranged together to be displayed in one picture screen of a display device.

7. 发明授权

US5181116A Television receiver with control of writing and reading of video memory 失效
标题翻译：具有视频存储器写入和读取控制的电视接收器
公开(公告)号：US5181116A
公开(公告)日：1993-01-19
申请号：US489509
申请日：1990-03-07
申请人： Nobufumi Nakagaki , Toshiyuki Kurita , Toshinori Murata , Kazuhiro Kaizaki , Sadao Kubota , Masanori Kamiya , Hiroshi Sekiya , Kenichi Fujiwara
发明人： Nobufumi Nakagaki , Toshiyuki Kurita , Toshinori Murata , Kazuhiro Kaizaki , Sadao Kubota , Masanori Kamiya , Hiroshi Sekiya , Kenichi Fujiwara
IPC分类号： H04N5/06 , H04N3/227 , H04N3/24 , H04N5/12 , H04N5/907 , H04N7/01
CPC分类号： H04N5/12 , H04N3/227
摘要： In a television receiver in which scanning for an incoming video signal is performed at a frequency n times as high as the input horizontal synchronous frequency by suitably controlling writing and reading on its video memory, the signals for writing and reading on the video memory unit are generated by a horizontal synchronization/deflection circuit. The horizontal synchronization/deflection circuit is arranged by having a clock generation/synchronous deflection circuit for generating reference signals to control the writing and reading on the video memory unit provided with a phase comparator such that a horizontal drive signal to drive a horizontal deflection circuit and a flyback pulse are brought in phase.
摘要翻译：在通过适当地控制其视频存储器上的写入和读取的情况下，以输入水平同步频率的n倍的频率执行输入视频信号的扫描的电视接收机中，用于在视频存储器单元上进行写入和读取的信号是由水平同步/偏转电路产生。水平同步/偏转电路通过具有产生参考信号的时钟产生/同步偏转电路来布置，以控制在具有相位比较器的视频存储器单元上的写入和读取，使得驱动水平偏转电路的水平驱动信号和回扫脉冲同时进入。

8. 发明授权

US4368461A Digital data processing device 失效
标题翻译：数字数据处理装置
公开(公告)号：US4368461A
公开(公告)日：1983-01-11
申请号：US212232
申请日：1980-12-02
申请人： Shigeru Komatsu , Kunihiko Nagai , Takuo Koyama , Tsuguji Tachiuchi , Mikiaki Kobayashi , Toshiyuki Kurita
发明人： Shigeru Komatsu , Kunihiko Nagai , Takuo Koyama , Tsuguji Tachiuchi , Mikiaki Kobayashi , Toshiyuki Kurita
IPC分类号： G09G5/36 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/34 , G09G1/02
CPC分类号： G09G5/001 , G09G5/02
摘要： A digital data processing device in which a color memory has a temporal data storage register at input/output interface thereof so that the data write-in or data read-out operations executed by a micro-processing unit (MPU) is always performed through the temporal storage register. When data read-out or write-in operation is made to a character memory at a certain address, the same operation is simultaneously carried out for the color memory at the corresponding address. Assuming that MPU reads out a certain display address of a display screen, a corresponding character code is fetched by MPU from the character memory, while the corresponding color code is transferred to the temporal storage register from the color memory. When MPU performs the write-in operation for another address of the display screen, the character code held by MPU until then is written in the character memory at a designated address, while the color data i.e. the contents currently held by the temporal storage register are written in the color memory at the address which corresponds to the designated address of the character memory. In this manner, the color data is simultaneously transferred through the software-based processing for transferring only the character code in appearance, whereby the transfer of the contents to be displayed on the display screen can be carried out with an enhanced efficiency.
摘要翻译：一种数字数据处理装置，其中色彩存储器在其输入/输出接口处具有时间数据存储寄存器，使得由微处理单元（MPU）执行的数据写入或数据读出操作总是通过临时存储寄存器。当对特定地址的字符存储器进行数据读出或写入操作时，对于相应地址的彩色存储器同时进行相同的操作。假设MPU读出显示屏幕的某个显示地址，则由MPU从字符存储器取出相应的字符代码，同时将相应的颜色代码从颜色存储器传送到临时存储寄存器。当MPU对显示画面的另一个地址执行写入操作时，由MPU保持的字符代码以指定地址写入字符存储器，而颜色数据即时间存储寄存器当前保持的内容是在对应于字符存储器的指定地址的地址处写入彩色存储器。以这种方式，通过基于软件的处理来同时传送彩色数据，用于仅传送字符代码的外观，从而能够以提高的效率进行显示在显示画面上的内容的传送。

9. 发明授权

US4329709A Solid-state color imaging device 失效
标题翻译：固态彩色成像装置
公开(公告)号：US4329709A
公开(公告)日：1982-05-11
申请号：US192998
申请日：1980-10-02
申请人： Michio Masuda , Hiroaki Nabeyama , Toshiyuki Kurita
发明人： Michio Masuda , Hiroaki Nabeyama , Toshiyuki Kurita
IPC分类号： H04N9/07 , H04N9/04
CPC分类号： H04N9/045
摘要： A solid-state color imaging device includes a plurality of different color filters arranged above photo-electric conversion elements arranged in matrix, such that each of chroma signals necessary for color reproduction includes the same spectrum of vertical smear component. A single memory is provided to store a vertical smear component included in one of the chroma signals necessary for the color reproduction. By subtracting a predetermined multiple of the output of the memory from the output signals on all of the chroma signal output lines, the vertical smear components appearing in all of the chroma signal output lines are eliminated.
摘要翻译：固体彩色成像装置包括布置在矩阵中的光电转换元件之上的多个不同的滤色器，使得颜色再现所需的每个色度信号包括相同的垂直污迹分量谱。提供单个存储器以存储包括在颜色再现所必需的色度信号之一中的垂直涂片成分。通过从所有色度信号输出线上的输出信号中减去存储器的输出的预定倍数，消除出现在所有色度信号输出行中的垂直污点分量。

10. 发明授权

US06625071B2 Memory circuit having block address switching function 失效
公开(公告)号：US06625071B2
公开(公告)日：2003-09-23
申请号：US10085065
申请日：2002-03-01
申请人： Mitsutaka Ikeda , Tsutomu Nakai , Koji Yamashita , Toshiyuki Kurita
发明人： Mitsutaka Ikeda , Tsutomu Nakai , Koji Yamashita , Toshiyuki Kurita
IPC分类号： G11C700
CPC分类号： G11C29/76 , G11C29/88
摘要： A memory circuit capable of salvaging defective cells, comprises a plurality of memory blocks each having a plurality of memory cells, a region which stores a block address of defective memory block that has defective cell, and a comparator circuit which compares the block address that is an object of access with the block address of the defective memory block, and detects access to the defective memory block, wherein in case where the comparator circuit detects access to the defective memory block, this defective memory block is replaced by the memory block that has the uppermost address (or lowermost address) among the plurality of memory blocks. In case where a plurality of defective memory blocks are present, the defective memory blocks are replaced with substitutive memory blocks having block addresses in order from the uppermost bit (or lowermost bit).

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