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1. 发明授权

US06486472B2 Inspecting system using electron beam and inspecting method using same 失效
标题翻译：使用电子束的检查系统和使用它的检查方法
公开(公告)号：US06486472B2
公开(公告)日：2002-11-26
申请号：US09943394
申请日：2001-08-30
申请人： Yasuhiro Gunji , Taku Ninomiya , Masatsugu Kametani , Masahiro Koyama , Kenjiro Yamamoto
发明人： Yasuhiro Gunji , Taku Ninomiya , Masatsugu Kametani , Masahiro Koyama , Kenjiro Yamamoto
IPC分类号： H01J37256
CPC分类号： H01J37/28 , H01J2237/2817
摘要： The present invention aims to prevent degradation in performance due to a change in image quality and deflection distortions or the like in the vicinity of both ends of a scan area and detect a defect in a sample such as a semiconductor wafer or the like with high accuracy when the defect is inspected by use of an electron beam image, and allow a monitor to confirm an image area to be checked. The present invention is provided with means for comparing and checking defects in the sample, based on an image signal in which the neighborhoods of both ends of horizontal and vertical scan areas are respectively deleted under control of a blanking signal and a vertical synchronizing signal.
摘要翻译：本发明旨在防止由于扫描区域两端附近的图像质量和偏转失真等的变化而导致的性能下降，并以高精度检测诸如半导体晶片等的样品中的缺陷当通过使用电子束图像检查缺陷时，并且允许监视器确认要检查的图像区域。本发明提供了用于基于在消隐信号和垂直同步信号的控制下分别删除水平和垂直扫描区域的两端的相邻区域的图像信号来比较和检查样本中的缺陷的装置。

2. 发明授权

US06580075B2 Charged particle beam scanning type automatic inspecting apparatus 有权
标题翻译：带电粒子束扫描式自动检测装置
公开(公告)号：US06580075B2
公开(公告)日：2003-06-17
申请号：US10251749
申请日：2002-09-23
申请人： Masatsugu Kametani , Kenjiro Yamamoto , Taku Ninomiya , Osamu Yamada , Katsuhisa Ike
发明人： Masatsugu Kametani , Kenjiro Yamamoto , Taku Ninomiya , Osamu Yamada , Katsuhisa Ike
IPC分类号： G01N2300
CPC分类号： H01J37/28 , H01J2237/2817
摘要： A charged particle beam scanning inspecting apparatus for irradiating a charged particle beam, fetching information of a subject to be inspected at a predetermined beam scanning position and performing an inspection by processing the information. The apparatus is a measurer which measures a scanning position of the beam and an inspection position on said inspection subject to calculate beam target coordinates corrected for an apparatus error, an error correction constant and a deflected distortion correction constant, and a deflection controller for scanning the beam. The deflection controller includes a deflection position operating circuit for performing an operation of the inspection position in a deflection coordinate system, a deflected distortion operating circuit. The deflection position operating circuit and deflected distortion operating circuit are constructed in a pipe line fashion.
摘要翻译：一种用于照射带电粒子束的带电粒子束扫描检查装置，在预定的束扫描位置获取要检查的对象的信息，并通过处理该信息进行检查。该装置是测量光束的扫描位置和所述检查对象上的检查位置的计量器，用于计算针对装置误差校正的光束目标坐标，误差校正常数和偏转失真校正常数，以及用于扫描光束。偏转控制器包括用于在偏转坐标系中执行检查位置的操作的偏转位置操作电路，偏转失真操作电路。偏转位置操作电路和偏转失真操作电路以管道方式构成。

3. 发明授权

US06538248B1 Charged particle beam scanning type automatic inspecting apparatus 有权
标题翻译：带电粒子束扫描式自动检测装置
公开(公告)号：US06538248B1
公开(公告)日：2003-03-25
申请号：US09398044
申请日：1999-09-17
申请人： Masatsugu Kametani , Kenjiro Yamamoto , Taku Ninomiya , Osamu Yamada , Katsuhisa Ike
发明人： Masatsugu Kametani , Kenjiro Yamamoto , Taku Ninomiya , Osamu Yamada , Katsuhisa Ike
IPC分类号： H01J3728
CPC分类号： H01J37/28 , H01J2237/2817
摘要： In order that the deflection scanning position can be corrected at a time point within a period for fetching information from a subject to be inspected and improvements in accuracy of chip comparison inspection and an inspection near the wafer outer periphery where distortion is large can be assured by correcting the inspection position and biased distortion at a high speed with high accuracy, a digital deflection control scheme is employed in which the deflection scanning signal and correction are all calculated digitally in a deflection controller for deflecting and controlling a charged particle beam irradiated onto a subject to be inspected and the digital value is sequentially converted into an analog value by a time-series train of digital control signal to form a deflection scanning waveform.
摘要翻译：为了可以在用于从要检查的对象取出信息的时间段内的时间点校正偏转扫描位置，并且可以通过提高芯片比较检查的精度和在失真很大的晶片外周边附近的检查来确保偏转扫描位置以高精度校正检查位置和偏置的失真，采用数字偏转控制方案，其中偏转扫描信号和校正都全部以偏转控制器数字计算，用于偏转和控制照射到被摄体上的带电粒子束并通过数字控制信号的时间序列序列将数字值顺序地转换为模拟值，以形成偏转扫描波形。

4. 发明授权

US5479635A Memory device including DRAMs for high-speed accessing 失效
标题翻译：存储器件包括用于高速存取的DRAM
公开(公告)号：US5479635A
公开(公告)日：1995-12-26
申请号：US282485
申请日：1994-08-01
申请人： Masatsugu Kametani
发明人： Masatsugu Kametani
IPC分类号： G06F9/34 , G06F12/02 , G06F12/06 , G11C7/10 , G11C11/406 , G11C11/4096 , G06F12/00 , G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G06F12/0215 , G06F12/06 , G06F9/34 , G11C11/4096 , G11C7/1018 , G11C7/1021
摘要： A memory device comprises a dynamic random access memory (DRAM) organized by page and a memory access devices. The DRAM corresponding to the pages is divided into a plurality of groups each constituted of pages for storing data which are unlikely to give rise to interference between pages. The DRAM of each group is constituted as a memory system which responds to page access. The memory access devices are provided separately for the memory system of each group. Each memory access device has a memory means which, in response to an access designating a page address of the memory system associated therewith, stores an old page address designated at least one access earlier, and judging means which, in response to said page address access, judges whether or not the new page address designated by said access coincides with said old page address stored in said storage means. Page access is conducted in accordance with the old address if the judging means judges that the old and new page addresses coincide and is conducted in accordance with the new address after changing the page to be accessed to said new page if the old and new page addresses do not coincide.
摘要翻译：存储器件包括由页面和存储器访问设备组织的动态随机存取存储器（DRAM）。对应于这些页面的DRAM被划分成多个组，每组由用于存储不太可能引起页之间干扰的数据的页组成。每个组的DRAM被构成为响应于页面访问的存储器系统。为每组的存储系统单独提供存储器访问设备。每个存储器访问设备具有存储装置，响应于指定与其相关联的存储器系统的寻址地址的访问，存储先前指定的至少一个访问的旧页地址，以及响应于所述页面地址访问的判定装置判断由所述访问指定的新页面地址是否与存储在所述存储装置中的所述旧页地址一致。如果旧页和新页地址，如果判断装置判断新页地址一致并且在将要被访问的页面改变为所述新页面之后根据新地址进行访问，则页面访问是根据旧地址进行的不重合

5. 发明授权

US5422834A Simulation method and system for simulating drive mechanism 失效
标题翻译：用于模拟驱动机制的仿真方法和系统
公开(公告)号：US5422834A
公开(公告)日：1995-06-06
申请号：US118206
申请日：1993-09-09
申请人： Toshihiko Horiuchi , Masaki Nakagawa , Masatsugu Kametani , Takao Konno
发明人： Toshihiko Horiuchi , Masaki Nakagawa , Masatsugu Kametani , Takao Konno
IPC分类号： G01M7/02 , G01M7/06 , G06G7/12
CPC分类号： G01M7/06 , G01M7/022
摘要： In place of a controlled object structure, a reaction force simulating actuator is connected to an actuator controlling the structure for recording a displacement at the connecting point. A reaction force at the connecting point after a given period of time is calculated by a digital computer on the basis of the measured value of the displacement and so forth and a known external force. The reaction force simulating actuator is actuated to realize the reaction force calculated value after the given period of time. Accordingly, since a load substantially corresponding to the reaction force from the controlled object structure is provided to a drive device, a test of the controlling drive device to be used in a condition difficult to realize can be performed under substantially similar conditions as in actual usage.
摘要翻译：代替受控对象结构，反作用力模拟致动器连接到控制用于在连接点处记录位移的结构的致动器。在数字计算机基于位移等的测量值和已知的外力来计算在给定时间段之后的连接点处的反作用力。启动反作用力模拟执行器，实现给定时间后的反作用力计算值。因此，由于将与受控对象结构的反作用力基本对应的载荷设置在驱动装置上，所以在实际使用条件下可以在与实际使用情况基本相同的条件下进行难以实现的控制驱动装置的试验。

6. 发明授权

US5361369A Synchronous method of, and apparatus for, allowing a processor to process a next task before synchronization between a predetermined group of processors 失效
标题翻译：用于允许处理器在预定处理器组之间的同步之前处理下一个任务的同步方法和装置
公开(公告)号：US5361369A
公开(公告)日：1994-11-01
申请号：US759529
申请日：1991-09-13
申请人： Masatsugu Kametani
发明人： Masatsugu Kametani
IPC分类号： G06F9/45 , G06F9/00
CPC分类号： G06F8/458
摘要： When a plurality of processors share a plurality of tasks and parallelly process the shared tasks, each of these processors outputs bit information for designating a processor in a group to which the processor belongs, when a currently executed task processing has been terminated, and the bit information is stored in a synchronous register disposed in each of the processors. When it is detected that all of processors in the same group have terminated task processings, each of these processors in the same group are supplied with a synchronization termination signal from the synchronous registers related thereto. Before all of the task processings have been terminated in the same group, any processors in the same group which have already terminated their task processings progress the execution of the next tasks until they access for the first time a data sharing circuit for holding data shared among the processors.
摘要翻译：当多个处理器共享多个任务并且并行地处理共享任务时，当当前执行的任务处理已被终止时，这些处理器中的每个处理器输出用于指定处理器所属组中的处理器的位信息，并且该位信息被存储在设置在每个处理器中的同步寄存器中。当检测到同一组中的所有处理器已经终止任务处理时，相同组中的这些处理器中的每一个被提供有与其相关的同步寄存器的同步终止信号。在所有任务处理已经在同一组中终止之前，已经终止其任务处理的同一组中的任何处理器进行下一任务的执行，直到它们首次访问用于保持数据共享的数据共享电路处理器。

7. 发明授权

US6161168A Shared memory system 失效
标题翻译：共享内存系统
公开(公告)号：US6161168A
公开(公告)日：2000-12-12
申请号：US165200
申请日：1998-10-02
申请人： Masatsugu Kametani
发明人： Masatsugu Kametani
IPC分类号： G06F15/17 , G06F12/00 , G06F12/06 , G06F15/167 , G06F15/16
CPC分类号： G06F15/17 , G06F15/167
摘要： A parallel processing system in which access contention of a read cycle from a processing unit side to a local shared memory and a write cycle from a shared bus system side on the local shared memory is reduced and a memory LSI which may be used in such unit are provided. The parallel processing system comprises a local shared memory between the processor and a shared bus. Address and data input means (WA and DI) for writing data to a memory cell and address input means (RA) and data output means (DO) for reading data are provided independently from each other to parallelize operations for reading from the processor side and for writing from the shared bus side.
摘要翻译：其中减少了从处理单元侧到本地共享存储器的读取周期的访问争用以及来自本地共享存储器上的共享总线系统侧的写入周期的并行处理系统，以及可以在该单元中使用的存储器LSI 被提供。并行处理系统包括处理器和共享总线之间的本地共享存储器。用于将数据写入存储单元的地址和数据输入装置（WA和DI）和用于读取数据的地址输入装置（RA）和数据输出装置（DO）彼此独立地提供以并行化从处理器侧读取的操作和从共享总线写入。

8. 发明授权

US5568617A Processor element having a plurality of processors which communicate with each other and selectively use a common bus 失效
标题翻译：处理器元件具有彼此通信并选择性地使用公共总线的多个处理器
公开(公告)号：US5568617A
公开(公告)日：1996-10-22
申请号：US182695
申请日：1994-01-13
申请人： Masatsugu Kametani
发明人： Masatsugu Kametani
IPC分类号： G06F9/38 , G06F13/364 , G06F15/16 , G06F15/167 , H01L21/98 , H01L25/065 , H01L29/06
CPC分类号： G06F9/3879 , G06F15/167 , G06F9/3877 , H01L25/0652 , H01L25/50 , H01L29/0657 , H01L2924/0002
摘要： A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU with associated local memories, a dual-port RAM accessible from said CPUs, and a common bus switch circuit for connecting any one of said CPUs to a common bus shared by said CPUs.
摘要翻译：用于构造单个处理器系统或多处理器系统的处理器包括在构成处理器的基本处理器元件内的两个CPU与相关联的本地存储器，可从所述CPU访问的双端口RAM以及用于连接任何一个的公共总线开关电路所述CPU由所述CPU共享的公共总线。

9. 发明授权

US5335336A Memory device having refresh mode returning previous page address for resumed page mode 失效
标题翻译：具有刷新模式的存储器件返回用于恢复页面模式的前一页地址
公开(公告)号：US5335336A
公开(公告)日：1994-08-02
申请号：US79852
申请日：1993-06-22
申请人： Masatsugu Kametani
发明人： Masatsugu Kametani
IPC分类号： G06F9/34 , G06F12/02 , G06F12/06 , G11C7/10 , G11C11/406 , G11C11/4096 , G06F12/00 , G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G06F12/0215 , G06F12/06 , G06F9/34 , G11C11/4096 , G11C7/1018 , G11C7/1021
摘要： A memory device comprises a dynamic random access memory (DRAM) organized by page and a memory access devices. The DRAM corresponding to the pages is divided into a plurality of groups each constituted of pages for storing data which are unlikely to give rise to interference between pages. The DRAM of each group is constituted as a memory system which responds to page access. The memory access devices are provided separately for the memory system of each group. Each memory access device has a memory means which, in response to an access designating a page address of the memory system associated therewith, stores an old page address designated at least one access earlier, and judging means which, in response to said page address access, judges whether or not the new page address designated by said access coincides with said old page address stored in said storage means. Page access is conducted in accordance with the old address if the judging means judges that the old and new page addresses coincide and is conducted in accordance with the new address after changing the page to be accessed to said new page if the old and new page addresses do not coincide.
摘要翻译：存储器件包括由页面和存储器访问设备组织的动态随机存取存储器（DRAM）。对应于这些页面的DRAM被划分成多个组，每组由用于存储不太可能引起页之间干扰的数据的页组成。每个组的DRAM被构成为响应于页面访问的存储器系统。为每组的存储系统单独提供存储器访问设备。每个存储器访问设备具有存储装置，响应于指定与其相关联的存储器系统的寻址地址的访问，存储先前指定的至少一个访问的旧页地址，以及响应于所述页面地址访问的判定装置判断由所述访问指定的新页面地址是否与存储在所述存储装置中的所述旧页地址一致。如果旧页和新页地址，如果判断装置判断新页地址一致并且在将要被访问的页面改变为所述新页面之后根据新地址进行访问，则页面访问是根据旧地址进行的不重合

10. 发明授权

US4870608A Method and apparatus for floating point operation 失效
标题翻译：浮点运算方法和装置
公开(公告)号：US4870608A
公开(公告)日：1989-09-26
申请号：US123279
申请日：1987-11-20
申请人： Masatsugu Kametani
发明人： Masatsugu Kametani
IPC分类号： G06F17/17 , G06F1/035 , G06F7/57 , G06F9/22
CPC分类号： G06F9/223 , G06F1/0356 , G06F7/483 , G06F2101/04
摘要： Method and apparatus for floating point operation for calculating an approximate solution in a given argument of a function. An operation unit for carrying out floating point logical operation and floating point multiplication, a first memory for storing data necessary for operation and data produced in a course of operation, a second memory for storing a microprogram for controlling a process of operation of the operation unit, a micro-sequencer for issuing a control command necessary for the operation unit to carry out the operation, in accordance with the microprogram, a third memory for storing a table of solutions of coefficient functions in the series polynomial approximate equation of the function including a coefficient function consisting of numeric logic operation or multiplication operation, and an address latch for designating an address of the solution of the series expansion corresponding to the given argument of the function in the third memory are provided. When the function is instructed and the corresponding argument are given, the micro-sequencer calculates the address in the table of solution of the coefficient function corresponding to the argument, loads the calculated address to the address latch and reads the solution of the coefficient function from the table and supplies it to the operation unit. The operation unit calculates the solution of the given argument of the function based on the solution of the coefficient function read from the table, in accordance with the control command from the micro-sequencer.
摘要翻译：用于计算函数给定参数中的近似解的浮点运算方法和装置。一种用于执行浮点逻辑运算和浮点乘法的操作单元，用于存储操作所需的数据的第一存储器和在操作过程中产生的数据，存储用于控制操作单元的操作处理的微程序的第二存储器，用于发出操作单元执行所述操作所需的控制命令的微定序器，根据该微程序，存储用于存储系数函数的解的表的第三存储器，所述第三存储器包括：a的函数的串联多项式近似方程式提供由数字逻辑运算或乘法运算组成的系数函数，以及用于指定与第三存储器中的函数的给定参数相对应的序列扩展的解的解的地址的地址锁存器。当指定功能并给出相应的参数时，微定序器计算与参数相对应的系数函数的解的表中的地址，将计算的地址加载到地址锁存器，并将系数函数的解从并将其提供给操作单元。操作单元根据来自微定序器的控制命令，基于从表读取的系数函数的解来计算函数的给定自变量的解。

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