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    • 3. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US07251184B2
    • 2007-07-31
    • US11400404
    • 2006-04-10
    • Shuji NakayaWataru AbeMitsuaki Hayashi
    • Shuji NakayaWataru AbeMitsuaki Hayashi
    • G11C8/00
    • G11C7/18G11C7/12G11C17/12
    • A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1 is connected to a power source voltage, and the source electrode of the first MOS transistor PD1 is connected via a fourth MOS transistor PD2 to the power source voltage. Since there is not a resistance between the main bit line MBL1 and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.
    • 提供一种具有分层位线结构并且即使在低电压下也能执行高速读取操作的半导体存储器件。 子阵列12包括用于对主位线MBL 1充电的第一MOS晶体管PD1和用于对子位线SBL 1 - 1充电的第二MOS晶体管PS 1。 第二MOS晶体管PS 1的源电极连接到电源电压,第一MOS晶体管PD1的源电极通过第四MOS晶体管PD2连接到电源电压。 由于在主位线MBL 1和子位线SBL 1 - 1之间没有电阻,如果使用晶体管来实现导通,则存在该位线之间的电阻,主位线 并且可以高速执行子位线的充电。
    • 4. 发明申请
    • Semiconductor memory device
    • 半导体存储器件
    • US20060120201A1
    • 2006-06-08
    • US11267195
    • 2005-11-07
    • Masakazu KurataMitsuaki Hayashi
    • Masakazu KurataMitsuaki Hayashi
    • G11C8/00
    • G11C17/12
    • According to a conventional semiconductor memory device, in a replica circuit composed of a plurality of dummy bit lines, an off leakage current of a transistor has been significantly increased with the advance of a semiconductor microfabrication technology, so that the dummy bit line has not been able to be charged to a desired potential due to the off leakage current when charging. As a result of this, since a charging period or a discharging period of the dummy bit line is also different from a desired period, the optimal operation timing may not be set. In a dummy memory cell array, in order to connect a drain region 21 and a first dummy bit line 25, the first dummy bit line 25 is connected via contact and via holes 28 through 30 and metal electrodes 23 and 24, while a second dummy bit line 46 does not contact to a drain region 47.
    • 根据传统的半导体存储器件,在由多个虚拟位线构成的复制电路中,随着半导体微细加工技术的发展,晶体管的截止漏电流已经显着增加,使得虚位线未被 能够在充电时由于断开的漏电流而被充电到期望的电位。 结果,由于虚拟位线的充电期间或放电期间也与期望的周期不同,所以可以不设定最佳​​的动作时机。 在虚拟存储单元阵列中,为了连接漏区21和第一虚位线25,第一虚位线25经由接触和通孔28至30和金属电极23和24连接,而第二虚位 位线46不与漏极区域47接触。