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1. 发明授权

US07382657B2 Semiconductor memory device having bit line precharge circuit controlled by address decoded signals 有权
标题翻译：具有由地址解码信号控制的位线预充电电路的半导体存储器件
公开(公告)号：US07382657B2
公开(公告)日：2008-06-03
申请号：US11151639
申请日：2005-06-14
申请人： Mitsuaki Hayashi , Wataru Abe , Shuji Nakaya , Masakazu Kurata
发明人： Mitsuaki Hayashi , Wataru Abe , Shuji Nakaya , Masakazu Kurata
IPC分类号： G11C16/06
CPC分类号： G11C7/12 , G11C17/12
摘要： A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.
摘要翻译：半导体存储器件包括存储单元阵列，补偿在所选位线产生的OFF漏电流的充电电路，具有对应于未选择位线上的电位的接地电位的复位电路，由多个位线组成的读电路的栅极连接到位线的晶体管，以及位线预充电电路，其对所选择的位线进行固定时间段的充电。作为采用这种结构的结果，不需要在读取电路和位线之间的充电路径上提供诸如列解码器的传输门，使得可以实现低电源电压操作而不受衬底偏置效应的影响。

2. 发明申请

US20060002212A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060002212A1
公开(公告)日：2006-01-05
申请号：US11025138
申请日：2004-12-30
申请人： Shuji Nakaya , Mitsuaki Hayashi , Masakazu Kurata
发明人： Shuji Nakaya , Mitsuaki Hayashi , Masakazu Kurata
IPC分类号： G11C7/00
CPC分类号： G11C17/12 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C17/14 , G11C29/1201 , G11C29/14 , G11C2029/1202 , G11C2029/1204
摘要： An output end and an inverted output end of a latch circuit that is connected to an output buffer circuit are switched with each other, and thereby, the relationship between the data of “0” or “1” and the drain of a memory cell is connected or not connected to a bit line is changed. In addition, an input of a sense amplifier is fixed at the grounding potential by means of a test control signal, and thereby, positive logic is confirmed in the case where the output of the output buffer circuit is “L,” and negative logic is confirmed in the case where the output of the output buffer circuit is “H.”
摘要翻译：连接到输出缓冲电路的锁存电路的输出端和反相输出端彼此切换，由此“0”或“1”的数据与存储单元的漏极之间的关系为连接或未连接到位线被更改。此外，读出放大器的输入通过测试控制信号固定在接地电位，从而在输出缓冲电路的输出为“L”的情况下确认正逻辑，而负逻辑为在输出缓冲电路的输出为“H”的情况下确认。

3. 发明申请

US20080175076A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20080175076A1
公开(公告)日：2008-07-24
申请号：US12054263
申请日：2008-03-24
申请人： Mitsuaki HAYASHI , Wataru Abe , Shuji Nakaya , Masakazu Kurata
发明人： Mitsuaki HAYASHI , Wataru Abe , Shuji Nakaya , Masakazu Kurata
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C17/12
摘要： A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.
摘要翻译：半导体存储器件包括存储单元阵列，补偿在所选位线产生的OFF漏电流的充电电路，具有对应于未选择位线上的电位的接地电位的复位电路，由多个位线组成的读电路的栅极连接到位线的晶体管，以及位线预充电电路，其对所选择的位线进行固定时间段的充电。作为采用这种结构的结果，不需要在读取电路和位线之间的充电路径上提供诸如列解码器的传输门，使得可以实现低电源电压操作而不受衬底偏置效应的影响。

4. 发明申请

US20060158942A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060158942A1
公开(公告)日：2006-07-20
申请号：US11151639
申请日：2005-06-14
申请人： Mitsuaki Hayashi , Wataru Abe , Shuji Nakaya , Masakazu Kurata
发明人： Mitsuaki Hayashi , Wataru Abe , Shuji Nakaya , Masakazu Kurata
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C17/12
摘要： A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.
摘要翻译：半导体存储器件包括存储单元阵列，补偿在所选位线产生的OFF漏电流的充电电路，具有对应于未选择位线上的电位的接地电位的复位电路，由多个位线组成的读电路的栅极连接到位线的晶体管，以及位线预充电电路，其对所选择的位线进行固定时间段的充电。作为采用这种结构的结果，不需要在读取电路和位线之间的充电路径上提供诸如列解码器的传输门，使得可以实现低电源电压操作而不受衬底偏置效应的影响。

5. 发明授权

US07110307B2 Semiconductor memory with a data holding circuit having two output terminals 有权
标题翻译：具有数据保持电路的半导体存储器具有两个输出端子
公开(公告)号：US07110307B2
公开(公告)日：2006-09-19
申请号：US11025138
申请日：2004-12-30
申请人： Shuji Nakaya , Mitsuaki Hayashi , Masakazu Kurata
发明人： Shuji Nakaya , Mitsuaki Hayashi , Masakazu Kurata
IPC分类号： G11C11/34
CPC分类号： G11C17/12 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C17/14 , G11C29/1201 , G11C29/14 , G11C2029/1202 , G11C2029/1204
摘要： An output end and an inverted output end of a latch circuit that is connected to an output buffer circuit are switched with each other, and thereby, the relationship between the data of “0” or “1” and the drain of a memory cell is connected or not connected to a bit line is changed. In addition, an input of a sense amplifier is fixed at the grounding potential by means of a test control signal, and thereby, positive logic is confirmed in the case where the output of the output buffer circuit is “L,” and negative logic is confirmed in the case where the output of the output buffer circuit is “H.”
摘要翻译：与输出缓冲电路连接的锁存电路的输出端和反相输出端彼此切换，由此“0”或“1”的数据与存储单元的漏极之间的关系为连接或未连接到位线被更改。此外，读出放大器的输入通过测试控制信号固定在接地电位，从而在输出缓冲电路的输出为“L”的情况下确认正逻辑，而负逻辑为在输出缓冲电路的输出为“H”的情况下确认。

6. 发明授权

US07639559B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07639559B2
公开(公告)日：2009-12-29
申请号：US11686892
申请日：2007-03-15
申请人： Masakazu Kurata , Mitsuaki Hayashi
发明人： Masakazu Kurata , Mitsuaki Hayashi
IPC分类号： G11C8/00
CPC分类号： G11C7/14 , G11C7/12 , G11C16/24 , G11C16/28
摘要： In a conventional semiconductor memory device, a replica circuit configured by using a dummy bit line has been unable to charge the dummy bit line to a desired potential due to off leak current. Consequently, the time required for charging or discharging the dummy bit line differs from the desired time, and therefore, it has been unable to set optimum operation timing. To solve these problems, a semiconductor memory device of the present invention includes a dummy memory cell array in which source lines of dummy memory cells are charged simultaneously by a charge circuit configured similarly to a dummy bit line charge circuit, thus suppressing off leak current and performing appropriate timing generation.
摘要翻译：在传统的半导体存储器件中，通过使用虚拟位线配置的复制电路由于断开的漏电流而不能将虚拟位线充电到期望的电位。因此，虚拟位线的充电或放电所需的时间与期望的时间不同，因此不能设定最佳的动作时机。为了解决这些问题，本发明的半导体存储器件包括：虚拟存储单元阵列，其中虚拟存储单元的源极线由与虚拟位线充电电路类似地构成的充电电路同时充电，从而抑制漏电流; 执行适当的定时生成。

7. 发明申请

US20060120201A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20060120201A1
公开(公告)日：2006-06-08
申请号：US11267195
申请日：2005-11-07
申请人： Masakazu Kurata , Mitsuaki Hayashi
发明人： Masakazu Kurata , Mitsuaki Hayashi
IPC分类号： G11C8/00
CPC分类号： G11C17/12
摘要： According to a conventional semiconductor memory device, in a replica circuit composed of a plurality of dummy bit lines, an off leakage current of a transistor has been significantly increased with the advance of a semiconductor microfabrication technology, so that the dummy bit line has not been able to be charged to a desired potential due to the off leakage current when charging. As a result of this, since a charging period or a discharging period of the dummy bit line is also different from a desired period, the optimal operation timing may not be set. In a dummy memory cell array, in order to connect a drain region 21 and a first dummy bit line 25, the first dummy bit line 25 is connected via contact and via holes 28 through 30 and metal electrodes 23 and 24, while a second dummy bit line 46 does not contact to a drain region 47.
摘要翻译：根据传统的半导体存储器件，在由多个虚拟位线构成的复制电路中，随着半导体微细加工技术的发展，晶体管的截止漏电流已经显着增加，使得虚位线未被能够在充电时由于断开的漏电流而被充电到期望的电位。结果，由于虚拟位线的充电期间或放电期间也与期望的周期不同，所以可以不设定最佳的动作时机。在虚拟存储单元阵列中，为了连接漏区21和第一虚位线25，第一虚位线25经由接触和通孔28至30和金属电极23和24连接，而第二虚位位线46不与漏极区域47接触。

8. 发明申请

US20070217246A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20070217246A1
公开(公告)日：2007-09-20
申请号：US11686892
申请日：2007-03-15
申请人： Masakazu Kurata , Mitsuaki Hayashi
发明人： Masakazu Kurata , Mitsuaki Hayashi
IPC分类号： G11C17/00 , G11C8/00
CPC分类号： G11C7/14 , G11C7/12 , G11C16/24 , G11C16/28
摘要： In a conventional semiconductor memory device, a replica circuit configured by using a dummy bit line has been unable to charge the dummy bit line to a desired potential due to off leak current. Consequently, the time required for charging or discharging the dummy bit line differs from the desired time, and therefore, it has been unable to set optimum operation timing. To solve these problems, a semiconductor memory device of the present invention includes a dummy memory cell array in which source lines of dummy memory cells are charged simultaneously by a charge circuit configured similarly to a dummy bit line charge circuit, thus suppressing off leak current and performing appropriate timing generation.
摘要翻译：在传统的半导体存储器件中，通过使用虚拟位线配置的复制电路由于断开的漏电流而不能将虚拟位线充电到期望的电位。因此，虚拟位线的充电或放电所需的时间与期望的时间不同，因此不能设定最佳的动作时机。为了解决这些问题，本发明的半导体存储器件包括：虚拟存储单元阵列，其中虚拟存储单元的源极线由与虚拟位线充电电路类似地构成的充电电路同时充电，从而抑制漏电流; 执行适当的定时生成。

9. 发明授权

US07722342B2 Pump apparatus and power steering 失效
标题翻译：泵装置和动力转向
公开(公告)号：US07722342B2
公开(公告)日：2010-05-25
申请号：US11684085
申请日：2007-03-09
申请人： Isamu Tsubono , Mitsuo Sasaki , Toru Takahashi , Masaaki Busujima , Masakazu Kurata , Yasuhito Nakakuki
发明人： Isamu Tsubono , Mitsuo Sasaki , Toru Takahashi , Masaaki Busujima , Masakazu Kurata , Yasuhito Nakakuki
IPC分类号： F01C1/02
CPC分类号： F04C2/102 , F04C2/084 , F04C2/18 , F04C15/0019 , F04C15/0026 , F04C2230/91
摘要： In order to realize cost reduction in a gear pump apparatus by reducing form accuracy of a gear while securing pump performance, a running-in coating is provided on a tooth sliding contact portion when forming a confinement area in at least one of gears of the gear pump apparatus. By this feature, the running-in coating is gradually worn away and deformed according to rotary drive of the pump, and thus it is possible to obtain an optimal gear form in meshing combinations of the gears. Further, it is possible to reduce leakage inside the pump to secure the pump performance even if the form accuracy of the gear is reduced for the sake of the cost reduction.
摘要翻译：为了通过在确保泵的性能的同时降低齿轮的形状精度来实现齿轮泵装置的成本降低，当在齿轮的齿轮中的至少一个齿轮中形成限制区域时，在齿滑动接触部分上设置进入涂层泵装置。通过该特征，随着泵的旋转驱动，流入式涂层逐渐磨损和变形，从而可以获得齿轮的啮合组合中的最佳齿轮形状。此外，为了降低成本，即使齿轮的形状精度降低，也可以减小泵内部的泄漏以确保泵的性能。

10. 发明授权

US07665569B2 Power steering system 失效
标题翻译：动力转向系统
公开(公告)号：US07665569B2
公开(公告)日：2010-02-23
申请号：US11430085
申请日：2006-05-09
申请人： Toshimitsu Sakaki , Masakazu Kurata , Toru Takahashi
发明人： Toshimitsu Sakaki , Masakazu Kurata , Toru Takahashi
IPC分类号： B62D5/06
CPC分类号： B62D5/065 , B62D5/064
摘要： A power steering system includes a hydraulic power cylinder having a first and a second hydraulic chambers, for assisting a steering force of a steering mechanism, a first and a second oil passages respectively connected to the first and second hydraulic chambers, a reversible pump discharging operating oil and providing oil pressure to the hydraulic power cylinder through the first and second oil passages, and a motor connected to the reversible pump and rotating the reversible pump in normal and reverse directions. A steering load detection unit detects a steering load of a steering wheel for steering of the steered road wheels, and a motor control unit outputs a control signal to the motor to bring an actual oil pressure generated by the reversible pump closer to a desired oil pressure determined based on the detected steering load. A discharge amount per rotation of the reversible pump is smaller than or equal to 5 cc.
摘要翻译：动力转向系统包括具有第一和第二液压室的液压动力缸，用于辅助转向机构的转向力，分别连接到第一和第二液压室的第一和第二油路，并通过第一和第二油路向液压动力缸提供油压，以及连接到可逆泵并且沿正向和反向旋转可逆泵的马达。转向负载检测单元检测用于转向车轮的转向的方向盘的转向负载，电动机控制单元向电动机输出控制信号，以使由可逆泵产生的实际油压更接近期望的油压基于检测到的转向负载确定。可逆泵的每旋转的排出量小于或等于5cc。

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