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1. 发明授权

US5867438A DRAM with reduced electric power consumption 失效
标题翻译： DRAM具有降低的电力消耗
公开(公告)号：US5867438A
公开(公告)日：1999-02-02
申请号：US726168
申请日：1996-10-04
申请人： Yukihiro Nomura , Yasuharu Satoh , Yoshihiro Takemae , Takaaki Furuyama , Mitsuhiro Nagao , Masahiro Niimi
发明人： Yukihiro Nomura , Yasuharu Satoh , Yoshihiro Takemae , Takaaki Furuyama , Mitsuhiro Nagao , Masahiro Niimi
IPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C7/00
CPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C5/143
摘要： A DRAM (dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.
摘要翻译：具有多个存储单元的DRAM（动态随机存取存储器）包括读取或写入存储单元的数据的数据读/写电路，刷新存储在存储单元中的数据的自刷新电路，以及供给单元数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于第一电压电平。

2. 发明授权

US6097658A DRAM with reduced electric power consumption 有权
标题翻译： DRAM具有降低的电力消耗
公开(公告)号：US6097658A
公开(公告)日：2000-08-01
申请号：US189148
申请日：1998-11-10
申请人： Yasuharu Satoh , Yoshihiro Takemae , Takaaki Furuyama , Mitsuhiro Nagao , Masahiro Niimi
发明人： Yasuharu Satoh , Yoshihiro Takemae , Takaaki Furuyama , Mitsuhiro Nagao , Masahiro Niimi
IPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C7/00
CPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C5/143
摘要： A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.
摘要翻译：具有多个存储单元的DRAM（动态随机存取存储器）包括数据读/写电路读取或写入存储单元的数据，自刷新电路刷新存储在存储单元中的数据，以及电源单元，数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于第一电压电平。

3. 发明授权

US5594699A DRAM with reduced electric power consumption 失效
标题翻译： DRAM具有降低的电力消耗
公开(公告)号：US5594699A
公开(公告)日：1997-01-14
申请号：US308105
申请日：1994-09-16
申请人： Yukihiro Nomura , Yasuharu Satoh , Yoshihiro Takemae , Takaaki Furuyama , Mitsuhiro Nagao , Masahiro Niimi
发明人： Yukihiro Nomura , Yasuharu Satoh , Yoshihiro Takemae , Takaaki Furuyama , Mitsuhiro Nagao , Masahiro Niimi
IPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C7/00
CPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C5/143
摘要： A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.
摘要翻译：具有多个存储单元的DRAM（动态随机存取存储器）包括数据读/写电路读取或写入存储单元的数据，自刷新电路刷新存储在存储单元中的数据，以及电源单元，数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于第一电压电平。

4. 发明申请

US20050185482A1 Semiconductor memory storage device and a redundancy control method therefor 有权
标题翻译：半导体存储器存储装置及其冗余控制方法
公开(公告)号：US20050185482A1
公开(公告)日：2005-08-25
申请号：US11061307
申请日：2005-02-18
申请人： Satoru Sugimoto , Takaaki Furuyama , Mitsuhiro Nagao
发明人： Satoru Sugimoto , Takaaki Furuyama , Mitsuhiro Nagao
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/81
摘要： An address identifying memory block is match-compared with address information stored in a to-be-remedied block memory section in a block redundancy judge section. A redundant block select signal is outputted from the block redundancy judge section by judgment of address match. A memory block column select section selects a memory block column having a redundant memory block irrespective of an address signal as the redundant block select signal is activated if block redundancy is activated to output a memory block column select signal. A column redundancy memory section selects address information of column redundancy relating a redundant memory block arranged in a memory block column in accordance with the memory block column select signal.
摘要翻译：地址识别存储器块与块冗余判断部分中存储在待修复块存储器部分中的地址信息进行匹配比较。通过地址匹配的判断从块冗余判断部分输出冗余块选择信号。如果块冗余被激活以输出存储块列选择信号，则存储块列选择部分选择具有冗余存储块而不管地址信号的存储块列，因为冗余块选择信号被激活。列冗余存储器部分根据存储器块列选择信号选择与排列在存储器块列中的冗余存储器块有关的列冗余的地址信息。

5. 发明授权

US06643758B2 Flash memory capable of changing bank configuration 失效
公开(公告)号：US06643758B2
公开(公告)日：2003-11-04
申请号：US09984357
申请日：2001-10-30
申请人： Takaaki Furuyama , Mitsuhiro Nagao
发明人： Takaaki Furuyama , Mitsuhiro Nagao
IPC分类号： G06F1200
CPC分类号： G11C16/08 , G06F12/0653 , G06F2212/2022 , G11C16/20
摘要： According to one aspect of the present invention, the flash memory comprises a memory region divided into a plurality of real banks, wherein from among the plurality of products which consists of a plurality of combinations of virtual banks having at least one real bank; and a combination of the top boot in which the most significant address is allocated to the boot bank having the boot sector and the bottom boot in which the least significant address is allocated to the boot bank, product information data are set in a product information record section, whereby any product can be configured.

6. 发明授权

US07068555B2 Semiconductor memory storage device and a redundancy control method therefor 有权
标题翻译：半导体存储器存储装置及其冗余控制方法
公开(公告)号：US07068555B2
公开(公告)日：2006-06-27
申请号：US11061307
申请日：2005-02-18
申请人： Satoru Sugimoto , Takaaki Furuyama , Mitsuhiro Nagao
发明人： Satoru Sugimoto , Takaaki Furuyama , Mitsuhiro Nagao
IPC分类号： G11C7/00
CPC分类号： G11C29/81
摘要： An address identifying memory block is match-compared with address information stored in a to-be-remedied block memory section in a block redundancy judge section. A redundant block select signal is outputted from the block redundancy judge section by judgment of address match. A memory block column select section selects a memory block column having a redundant memory block irrespective of an address signal as the redundant block select signal is activated if block redundancy is activated to output a memory block column select signal. A column redundancy memory section selects address information of column redundancy relating a redundant memory block arranged in a memory block column in accordance with the memory block column select signal.
摘要翻译：地址识别存储器块与块冗余判断部分中存储在待修复块存储器部分中的地址信息进行匹配比较。通过地址匹配的判断从块冗余判断部分输出冗余块选择信号。如果块冗余被激活以输出存储块列选择信号，则存储块列选择部分选择具有冗余存储块而不管地址信号的存储块列，因为冗余块选择信号被激活。列冗余存储器部分根据存储器块列选择信号选择与排列在存储器块列中的冗余存储器块有关的列冗余的地址信息。

7. 发明授权

US07564720B2 Nonvolatile storage and erase control 有权
标题翻译：非易失性存储和擦除控制
公开(公告)号：US07564720B2
公开(公告)日：2009-07-21
申请号：US11879989
申请日：2007-07-18
申请人： Mitsuhiro Nagao , Masahiro Niimi , Kenji Nagai
发明人： Mitsuhiro Nagao , Masahiro Niimi , Kenji Nagai
IPC分类号： G11C11/03
CPC分类号： G11C16/16 , G11C8/16 , G11C11/412
摘要： A nonvolatile storage including a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased; a write amplifier for writing the erase setting information in the volatile memory cell array; a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of the erasing operation; and a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of readout operation.
摘要翻译：一种非易失性存储器，包括在擦除操作中用作一个单元的多个块，并且连续执行多个擦除操作，所述非易失性存储器包括：易失性存储单元阵列，用于存储关于每个块的擦除设置信息，所述信息指示是否其关联块是要擦除的目标; 写入放大器，用于将所述擦除设置信息写入所述易失性存储单元阵列; 第一读出放大器，用于在擦除操作开始时从易失性存储单元阵列读出目标块上的擦除设置信息; 以及第二读出放大器，用于在读出操作开始时从易失性存储单元阵列读出目标块上的擦除设置信息。

8. 发明申请

US20080049503A1 Nonvolatile storage and erase control 有权
标题翻译：非易失性存储和擦除控制
公开(公告)号：US20080049503A1
公开(公告)日：2008-02-28
申请号：US11879989
申请日：2007-07-18
申请人： Mitsuhiro Nagao , Masahiro Niimi , Kenji Nagai
发明人： Mitsuhiro Nagao , Masahiro Niimi , Kenji Nagai
IPC分类号： G11C11/34 , G11C16/02
CPC分类号： G11C16/16 , G11C8/16 , G11C11/412
摘要： A nonvolatile storage is disclosed which has a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased; a write amplifier for writing the erase setting information in the volatile memory cell array; a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of the erasing operation; and a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of readout operation.
摘要翻译：公开了一种非易失性存储器，其具有在擦除操作中作为一个单元的多个块，并且连续执行多个擦除操作，所述非易失性存储器包括：易失性存储单元阵列，用于存储关于每个块的擦除设置信息，所述信息指示其关联块是否是要擦除的目标; 写入放大器，用于将所述擦除设置信息写入所述易失性存储单元阵列; 第一读出放大器，用于在擦除操作开始时从易失性存储单元阵列读出目标块上的擦除设置信息; 以及第二读出放大器，用于在读出操作开始时从易失性存储单元阵列读出目标块上的擦除设置信息。

9. 发明申请

US20080155217A1 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US20080155217A1
公开(公告)日：2008-06-26
申请号：US11644161
申请日：2006-12-22
申请人： Kenta Kato , Masahiko Okura , Kenji Shibata , Mitsuhiro Nagao , Stewart Wang
发明人： Kenta Kato , Masahiko Okura , Kenji Shibata , Mitsuhiro Nagao , Stewart Wang
IPC分类号： G06F12/14
CPC分类号： G06F12/1425 , G06F2212/2022
摘要： A semiconductor device includes: a memory cell array that includes non-volatile memory cells; a first memory region and a second memory region that are located in the memory cell array, the first memory region being protected during a protecting period, the second memory region being not protected; an address change circuit that changes an address in an address space of the first memory region and the second memory region in the memory cell array, to an address in an address space of the second memory region, during the protecting period; and a control circuit that prohibits access to the first memory region, and allows access to the second region, during the protecting period.
摘要翻译：半导体器件包括：包括非易失性存储器单元的存储单元阵列; 位于所述存储单元阵列中的第一存储器区域和第二存储器区域，所述第一存储器区域在保护期间被保护，所述第二存储器区域不被保护; 在保护期间，将存储单元阵列中的第一存储器区域和第二存储器区域的地址空间中的地址改变为第二存储器区域的地址空间中的地址的地址改变电路; 以及控制电路，其在保护期间禁止对第一存储区域的访问，并允许访问第二区域。

10. 发明授权

US07934051B2 Program and erase disabling control of WPCAM by double controls 有权
标题翻译：通过双控制来编程和擦除WPCAM的禁用控制
公开(公告)号：US07934051B2
公开(公告)日：2011-04-26
申请号：US12012390
申请日：2008-02-01
申请人： Kenji Shibata , Masahiko Okura , Mitsuhiro Nagao
发明人： Kenji Shibata , Masahiko Okura , Mitsuhiro Nagao
IPC分类号： G06F12/00
CPC分类号： G11C16/22
摘要： The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions that include nonvolatile memory cells; program prohibition information units, the program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in a plurality of memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect a memory region, the memory region is one of the plurality of corresponding memory regions, based on first prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, based on second prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region.
摘要翻译：本发明提供半导体器件和控制半导体器件的方法，该半导体器件包括包括非易失性存储器单元的存储区域; 程序禁止信息单元，程序禁止信息单元存储要用于确定是否禁止或允许在对应于程序禁止信息单元的多个存储器区域中进行编程的程序禁止信息; 第一禁止信息控制电路，禁止将程序禁止信息从程序禁止状态改变为允许相对于存储区域的状态的程序，所述存储区域是所述多个对应的存储区域中的一个，基于第一禁止信息用于确定是否禁止将程序禁止信息从程序禁止状态改变为相对于对应的存储区域的程序允许状态; 以及第二禁止信息控制电路，其基于第二禁止信息来禁止程序禁止信息从允许状态到相对于存储区域的程序禁止状态的程序的改变，所述第二禁止信息控制电路用于确定是否禁止改变程序禁止信息从允许状态到相对于对应的存储器区域的程序禁止状态的程序。

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