专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06427197B1 Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations 有权
标题翻译：半导体存储器件与时钟信号同步工作，用于高速数据写入和数据读取操作
公开(公告)号：US06427197B1
公开(公告)日：2002-07-30
申请号：US09394891
申请日：1999-09-13
申请人： Yasuharu Sato , Tadao Aikawa , Shinya Fujioka , Waichiro Fujieda , Hitoshi Ikeda , Hiroyuki Kobayashi
发明人： Yasuharu Sato , Tadao Aikawa , Shinya Fujioka , Waichiro Fujieda , Hitoshi Ikeda , Hiroyuki Kobayashi
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C7/1039
摘要： The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length. When writing successively or reading successively, moreover, the command cycle can made short irrespective of the burst length.
摘要翻译：本发明是一种存储电路，用于响应于写命令，写入根据突发长度确定的指定数量的写入数据，包括：第一级，用于与第一级同时输入，然后保持行地址和列地址写命令第二级具有经由流水线开关连接到第一级的存储器核，其中行地址和列地址被解码，字线和检测放大器被激活; 用于串行输入写入数据并且将写入数据并行地发送到存储器核心的第三级; 以及串行数据检测电路，用于在输入了规定数量的写入数据之后，产生用于使流水线开关导通的写入流水线控制信号。根据本发明，在呈现流水线结构的FCRAM中，可以在以突发长度安全地取出写入数据之后激活第二级中的存储器核心。此外，当连续写入或连续读取时，无论突发长度如何，命令循环可以变短。

2. 发明授权

US06754126B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06754126B2
公开(公告)日：2004-06-22
申请号：US10106597
申请日：2002-03-27
申请人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
发明人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C8/12 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4087 , G11C2211/4061 , G11C2211/4062
摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
摘要翻译：形成多个第一存储块和用于再现第一存储块的数据的第二存储块。当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。因此，可以在不被用户识别的情况下进行刷新操作。即，可以提供用户友好的半导体存储器。

3. 发明授权

US06731553B2 Memory circuit having compressed testing function 有权
标题翻译：存储电路具有压缩测试功能
公开(公告)号：US06731553B2
公开(公告)日：2004-05-04
申请号：US10270196
申请日：2002-10-15
申请人： Shinya Fujioka , Waichiro Fujieda , Kota Hara
发明人： Shinya Fujioka , Waichiro Fujieda , Kota Hara
IPC分类号： G11C700
CPC分类号： G11C29/40
摘要： A multi-bit output configuration memory circuit comprises: a memory core having a normal cell array and a redundant cell array, which have a plurality of memory cells; N output terminals which respectively output N-bit output read out from the memory core; an output circuit provided between the output terminals and the memory core, which detects whether each L-bit output of the N-bit output (N=L×M) read out from said memory core matches or not and outputs a compressed output which becomes the output data in the event of a match while becomes a third state in the event of a non-match, to a first output terminal of the N output terminals. Responding to each of a plurality of test commands or the test control signals of the external terminals, the compressed output of the M groups of L-bit output is outputted in time shared.
摘要翻译：多比特输出配置存储器电路包括：具有正常单元阵列的存储器核心和具有多个存储单元的冗余单元阵列; N个输出端子，分别输出从存储器芯读出的N位输出; 输出电路，设置在输出端子和存储器核心之间，其检测从所述存储器芯片读出的N位输出（N = L×M）的每个L位输出是否匹配，并输出成为输出的压缩输出在匹配的情况下的数据在不匹配的情况下变为第三状态时，输出到N个输出端的第一输出端。响应多个测试命令或外部终端的测试控制信号中的每一个，M个组的L位输出的压缩输出以时间共享的形式被输出。

4. 发明授权

US06477093B2 Semiconductor memory and method of operating same 有权
公开(公告)号：US06477093B2
公开(公告)日：2002-11-05
申请号：US09901628
申请日：2001-07-11
申请人： Yoshiaki Okuyama , Shinya Fujioka , Waichiro Fujieda
发明人： Yoshiaki Okuyama , Shinya Fujioka , Waichiro Fujieda
IPC分类号： G11C800
CPC分类号： G11C8/06 , G11C8/00
摘要： An address signal is transmited to a decoder before the activation of a control signal operating a memory cell. Here, the decoder is inactivated. Subsequently, after the activation of the control signal, the reception of a new address signal is inhibited, and the decoder is activated at the same time. Therefore, the decoder starts operating at an earlier timing of the operating cycle, outputting a decoding signal. This means reduction in access time. Moreover, the reception of a new address signal is inhibited after the activation of the control signal. This prevents the decoder from decoding incorrect address signals ascribable to noises and the like, thereby avoiding malfunctions.

5. 发明授权

US07032142B2 Memory circuit having parity cell array 失效
公开(公告)号：US07032142B2
公开(公告)日：2006-04-18
申请号：US10271533
申请日：2002-10-17
申请人： Shinya Fujioka , Waichiro Fujieda , Kota Hara , Toru Koga , Katsuhiro Mori
发明人： Shinya Fujioka , Waichiro Fujieda , Kota Hara , Toru Koga , Katsuhiro Mori
IPC分类号： G11C29/00 , G11C7/00 , G06F11/00
CPC分类号： G11C29/42 , G06F11/106 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C2211/4062
摘要： A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.

6. 发明授权

US06545924B2 Semiconductor memory device 有权
公开(公告)号：US06545924B2
公开(公告)日：2003-04-08
申请号：US09929357
申请日：2001-08-15
申请人： Waichiro Fujieda , Shinya Fujioka
发明人： Waichiro Fujieda , Shinya Fujioka
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A semiconductor memory device having a self-refresh function includes a detection circuit detecting a change of an output enable signal and generating a state transition detection signal, and a decision circuit comparing the state transition detection signal and a refresh request signal internally generated and generating a signal that indicates a corresponding circuit operation.

7. 发明授权

US07358718B2 Semiconductor device and electronics device 有权
标题翻译：半导体器件和电子器件
公开(公告)号：US07358718B2
公开(公告)日：2008-04-15
申请号：US11434736
申请日：2006-05-17
申请人： Waichiro Fujieda
发明人： Waichiro Fujieda
IPC分类号： G01R31/26
CPC分类号： G01R31/3008 , G01R31/31721
摘要： A plurality of switch circuits are disposed so as to correspond to a plurality of circuit blocks, respectively. Each of the plurality of switch circuits is connected between a power supply terminal of a corresponding circuit block and a power supply line. A setting circuit is disposed to set each of the plurality of switch circuits to be in a valid or invalid state. A switch control circuit turns on each of the plurality of switch circuits according to a first control signal for indicating an operation state of the plurality of circuit blocks when each of the plurality of switch circuits is set in a valid state by the setting circuit and turns on each of the plurality of switch circuits regardless of the first control signal when each of the plurality of switch circuits is set in an invalid state by the setting circuit.
摘要翻译：多个开关电路分别设置成对应于多个电路块。多个开关电路中的每一个连接在相应的电路块的电源端子和电源线之间。设置电路以将多个开关电路中的每一个设置为有效或无效状态。开关控制电路根据用于指示多个电路块的操作状态的第一控制信号打开多个开关电路中的每一个，当多个开关电路中的每一个由设置电路设置在有效状态并转动时在所述多个开关电路中的每一个在所述多个开关电路中的每一个被所述设置电路设置为无效状态时，与所述第一控制信号无关。

8. 发明申请

US20110090752A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20110090752A1
公开(公告)日：2011-04-21
申请号：US12923981
申请日：2010-10-19
申请人： Waichiro Fujieda
发明人： Waichiro Fujieda
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C17/123
摘要： There is provided a semiconductor memory device including: plural memory cells; a selection signal outputting section; a first precharging section that precharges a potential of a data line that outputs, to an exterior, a signal of a level corresponding to data stored in the memory cell; and a bit line selecting section that has, per bit line, a bit line selecting section that comprises (1) a second precharging section, (2) a potential lowering section, and (3) a third precharging section connected to the bit line selection line and the bit line between the second precharging section and a connection point at which the potential lowering section is connected to the bit line, and when the non-selection signal is inputted, the third precharging section precharges the bit line between the second precharging section and the connection point at which the potential lowering section is connected to the bit line.
摘要翻译：提供了一种半导体存储器件，包括：多个存储单元; 选择信号输出部; 预先充电数据线的电位的第一预充电部分，其向外部输出与存储在存储单元中的数据相对应的电平的信号; 以及位线选择部分，每个位线具有位线选择部分，该位线选择部分包括：（1）第二预充电部分，（2）电位降低部分;以及（3）连接到位线选择的第三预充电部分以及第二预充电部分和电位降低部分连接到位线的连接点之间的位线，并且当输入非选择信号时，第三预充电部分预充电第二预充电部分之间的位线以及电位降低部分连接到位线的连接点。

9. 发明授权

US08254193B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08254193B2
公开(公告)日：2012-08-28
申请号：US12923981
申请日：2010-10-19
申请人： Waichiro Fujieda
发明人： Waichiro Fujieda
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C17/123
摘要： There is provided a semiconductor memory device including: plural memory cells; a selection signal outputting section; a first precharging section that precharges a potential of a data line that outputs, to an exterior, a signal of a level corresponding to data stored in the memory cell; and a bit line selecting section that has, per bit line, a bit line selecting section that comprises (1) a second precharging section, (2) a potential lowering section, and (3) a third precharging section connected to the bit line selection line and the bit line between the second precharging section and a connection point at which the potential lowering section is connected to the bit line, and when the non-selection signal is inputted, the third precharging section precharges the bit line between the second precharging section and the connection point at which the potential lowering section is connected to the bit line.
摘要翻译：提供了一种半导体存储器件，包括：多个存储单元; 选择信号输出部; 预先充电数据线的电位的第一预充电部分，其向外部输出与存储在存储单元中的数据相对应的电平的信号; 以及位线选择部分，每个位线具有位线选择部分，该位线选择部分包括：（1）第二预充电部分，（2）电位降低部分;以及（3）连接到位线选择的第三预充电部分以及第二预充电部分和电位降低部分连接到位线的连接点之间的位线，并且当输入非选择信号时，第三预充电部分预充电第二预充电部分之间的位线以及电位降低部分连接到位线的连接点。

10. 发明授权

US07420860B2 Semiconductor memory having a dummy signal line connected to dummy memory cell 有权
标题翻译：具有连接到虚拟存储单元的虚拟信号线的半导体存储器
公开(公告)号：US07420860B2
公开(公告)日：2008-09-02
申请号：US11707128
申请日：2007-02-16
申请人： Shinichi Yamada , Waichiro Fujieda , Shinichiroh Ikemasu
发明人： Shinichi Yamada , Waichiro Fujieda , Shinichiroh Ikemasu
IPC分类号： G11C7/00
CPC分类号： G11C7/14 , G11C11/401 , G11C11/4099 , G11C29/24 , G11C29/50 , G11C2029/5006
摘要： First dummy memory cells connected to a first dummy signal line have the same shape and characteristics as those of a real memory cell. The first dummy memory cells are arranged to be adjacent to outermost real memory cells. A voltage setting circuit changes the voltage of the first dummy signal line from a first voltage to a second voltage in order to write test data onto the first dummy memory cell during a test mode. By writing data of a logic opposite to that of the test data onto the real memory cell adjacent to the first dummy memory cell by means of an operation control circuit, a leak failure that may occur between the first dummy memory cell and the real memory cell adjacent thereto can be checked.
摘要翻译：连接到第一虚拟信号线的第一虚拟存储器单元具有与实际存储单元相同的形状和特性。第一虚拟存储器单元布置成与最外面的真实存储单元相邻。电压设定电路将第一虚拟信号线的电压从第一电压改变为第二电压，以便在测试模式期间将测试数据写入第一虚拟存储器单元。通过使用操作控制电路将与测试数据的逻辑相反的逻辑的数据写入与第一虚拟存储单元相邻的实际存储单元上，可能发生在第一虚拟存储单元和实际存储单元之间的泄漏故障可以检查相邻的位置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式