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1. 发明申请

US20110199790A1 BACKLIGHT UNIT AND DISPLAY DEVICE INCLUDING THE SAME 有权
标题翻译：背光单元和包括其的显示装置
公开(公告)号：US20110199790A1
公开(公告)日：2011-08-18
申请号：US12958452
申请日：2010-12-02
申请人： Kenichi MURAKOSHI , Tsuyoshi Ono , Hidekazu Fujii , Yasuaki Hirano , Makoto Hirota
发明人： Kenichi MURAKOSHI , Tsuyoshi Ono , Hidekazu Fujii , Yasuaki Hirano , Makoto Hirota
IPC分类号： F21V8/00
CPC分类号： G02B6/0068 , G02B6/0073 , G02B6/0083 , G02F1/133603 , G02F1/133611 , G02F1/133615
摘要： Provided is a backlight unit capable of reducing luminance unevenness. The backlight unit includes a plurality of dot light sources and a light guide plate in which a predetermined side surface serves as a light incident surface for introducing light from the plurality of dot light sources. The plurality of dot light sources are classified into a first light source group and a second light source group. A mount point of the first light source group and a mount point of the second light source group are displaced from each other in a thickness direction of the light guide plate. A total luminance of the first light source group is higher than a total luminance of the second light source group.
摘要翻译：提供能够降低亮度不均匀性的背光单元。背光单元包括多个点光源和导光板，其中预定侧表面用作用于引入来自多个点光源的光的光入射表面。多个点光源分为第一光源组和第二光源组。第一光源组的安装点和第二光源组的安装点在导光板的厚度方向上彼此偏移。第一光源组的总亮度高于第二光源组的总亮度。

2. 发明授权

US07038951B2 Non-volatile semiconductor memory device and erasing control method thereof 失效
标题翻译：非易失性半导体存储器件及其擦除控制方法
公开(公告)号：US07038951B2
公开(公告)日：2006-05-02
申请号：US10866442
申请日：2004-06-10
申请人： Yasuaki Hirano , Shuichiro Kouchi
发明人： Yasuaki Hirano , Shuichiro Kouchi
IPC分类号： G11C16/04
CPC分类号： G11C16/3477 , G11C16/16 , G11C16/3445 , G11C16/3459 , G11C16/3468
摘要： A non-volatile semiconductor memory device includes a memory cell array including a plurality of memory cells, wherein information is writable to each of the plurality of memory cells and information is erasable from each of the plurality of memory cells, and the plurality of memory cells are grouped into at least one memory block; and a write and erasing section for performing a program write operation to a prescribed memory cell in one memory block in a prescribed voltage condition and for performing an erasing operation with respect to the memory cells in the one memory block, wherein the write and erasing section performs a pre-erasing write operation to the memory cells in the one memory block in a voltage condition, which is different from the prescribed voltage condition, before the erasing operation is performed with respect to the memory cells in the one memory block.
摘要翻译：非挥发性半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元，其中信息可写入多个存储单元中的每一个，并且信息可从多个存储单元中的每一个擦除，并且多个存储单元被分组成至少一个存储块; 以及写入和擦除部分，用于以规定的电压条件对一个存储器块中的规定的存储器单元执行程序写入操作，并且对于所述一个存储器块中的存储器单元执行擦除操作，其中写入和擦除部分在相对于一个存储块中的存储单元执行擦除操作之前，在与规定电压条件不同的电压条件下，对一个存储块中的存储单元执行预擦除写入操作。

3. 发明授权

US6072722A Method of driving a nonvolatile semiconductor storage device 失效
标题翻译：驱动非易失性半导体存储装置的方法
公开(公告)号：US6072722A
公开(公告)日：2000-06-06
申请号：US111664
申请日：1998-07-08
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： G11C16/04 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/00
CPC分类号： G11C16/16 , G11C16/10
摘要： For programming data "0", a reference voltage Vss (e.g., 0 V) is applied to a drain and a source of a memory cell to be programmed via a corresponding main bit line, a corresponding select transistor, and a corresponding local bit line, while a second voltage Vpp (e.g., 15 V) is applied to a control gate of the memory cell via a word line connected with the memory cell. As a result, electrons are injected from the drain, source and channel region to a floating gate of the memory cell via its tunnel oxide. For erasing the memory cell, a third voltage Vds (e.g., 0-6 V) is applied to a semiconductor substrate of the memory cell and a fourth voltage Vneg (e.g., -10 V) is applied to the control gate via the word line. At this time, the third voltage is also applied to the source and drain. Alternatively, the source and drain of the memory cell are placed in a floating state. Consequently, electrons are ejected from the floating gate to the channel region via the tunnel oxide.
摘要翻译：对于编程数据“0”，将参考电压Vss（例如，0V）施加到要通过相应的主位线，相应的选择晶体管和相应的局部位线被编程的存储器单元的漏极和源极而第二电压Vpp（例如，15V）经由与存储单元连接的字线被施加到存储器单元的控制栅极。结果，电子从漏极，源极和沟道区域经由其隧道氧化物注入到存储器单元的浮置栅极。为了擦除存储单元，将第三电压Vds（例如，0-6V）施加到存储单元的半导体衬底，并且通过字线将第四电压Vneg（例如，-10V）施加到控制栅极。此时，第三电压也施加到源极和漏极。或者，存储器单元的源极和漏极被置于浮置状态。因此，电子通过隧道氧化物从浮动栅极喷射到沟道区。

4. 发明申请

US20050157555A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050157555A1
公开(公告)日：2005-07-21
申请号：US10760351
申请日：2004-01-21
申请人： Tsuyoshi Ono , Yasuaki Hirano , Masahiko Watanabe , Sau Wong
发明人： Tsuyoshi Ono , Yasuaki Hirano , Masahiko Watanabe , Sau Wong
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： In a nonvolatile floating-gate semiconductor memory device, a word line voltage supply circuit is configured to be able to apply gate voltages to the same memory cells such that the gate voltage applied at and after the second time is different from the gate voltage applied at the first time. At least one of the word line voltage supply circuit and the bit line voltage supply circuit is set to be able to apply a voltage to the same memory cells for a longer application period at the first time than at and after the second time. With this configuration, the threshold voltage distribution of the memory cells is controlled to be narrow.
摘要翻译：在非易失性浮栅半导体存储器件中，字线电压供给电路被配置为能够向相同的存储单元施加栅极电压，使得在第二时间施加的栅极电压与施加在第二时间的栅极电压不同第一次。字线电压供给电路和位线电压供给电路中的至少一个被设置为能够在第一时间比在第二时间和之后向相同存储器单元施加电压较长的施加周期。利用这种配置，将存储单元的阈值电压分布控制得很窄。

5. 发明授权

US06714459B2 Nonvolatile semiconductor memory device and method of detecting overerased cell 有权
标题翻译：非易失性半导体存储器件及其检测方法
公开(公告)号：US06714459B2
公开(公告)日：2004-03-30
申请号：US10241752
申请日：2002-09-12
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/28 , G11C16/3404
摘要： In a nonvolatile semiconductor memory device, overerase-verify in an erase operation is conducted in units of bit lines in a batch. A cell current of a reference cell and voltage applied to a word line of a main cell are set so as to have a detection level at which there can be one or no memory cell having a threshold voltage of 0.5 V at time of one overerase-verify operation and a leak current of an unselected memory cell can be 1 &mgr; A or lower in a normal operation. Thus, the number of verify times in the overerase-verify is reduced to shorten period of time in the overerase-verify and thereby achieve high-speed erase. Furthermore, a cell current can be reduced to achieve lower power consumption.
摘要翻译：在非易失性半导体存储器件中，在擦除操作中过度验证以批次中的位线为单位进行。参考单元的单元电流和施加到主单元的字线的电压被设置为具有检测电平，在该检测电平处可以存在一个或不存在阈值电压为0.5V的存储单元，验证操作，并且未选择的存储单元的泄漏电流在正常操作中可以为1μA或更低。因此，过度验证中的验证次数减少，以缩短过度验证中的时间段，从而实现高速擦除。此外，可以减小电池电流以实现更低的功耗。

6. 发明授权

US06331949B1 Circuit for storing and latching defective address data for a nonvolatile semiconductor memory device having redundant function 有权
标题翻译：用于存储和锁存具有冗余功能的非易失性半导体存储器件的不良地址数据的电路
公开(公告)号：US06331949B1
公开(公告)日：2001-12-18
申请号：US09745526
申请日：2000-12-26
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： G11C1606
CPC分类号： G11C29/789 , G11C16/0441 , G11C29/44
摘要： A circuit for storing and latching defective address data representing an address of a defective portion occurring in a memory cell array of a nonvolatile semiconductor memory device having a redundant function. The circuit includes floating gate field effect transistors and latch circuits. Each floating gate field effect transistor assumes one of a high-threshold state and a low-threshold state, and has a threshold of 0 volts or less (e.g. 0 to −2.5 volts) when in the low-threshold state.
摘要翻译：一种用于存储和锁存表示在具有冗余功能的非易失性半导体存储器件的存储单元阵列中出现的缺陷部分的地址的缺陷地址数据的电路。该电路包括浮栅场效应晶体管和锁存电路。每个浮置栅极场效应晶体管呈现高阈值状态和低阈值状态之一，并且当处于低阈值状态时具有0伏特或更小（例如0至-2.5伏特）的阈值。

7. 发明授权

US5652450A Nonvolatile semiconductor storage device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5652450A
公开(公告)日：1997-07-29
申请号：US684585
申请日：1996-07-19
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： G11C17/00 , G11C8/08 , G11C16/02 , G11C16/06 , G11C16/08 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/11526 , G11C16/08 , G11C8/08 , H01L27/11546
摘要： According to the present invention, a nonvolatile semiconductor storage device for applying to each word line either one of a selected voltage and a non-selected voltage, corresponding to a selection state and a non-selection state, respectively, is provided. The selection state or the non-selection state is selected in accordance with an address signal in each operational mode. The nonvolatile semiconductor storage device includes: a plurality of applied voltage decoders operating in accordance with an applied voltage selection state or an applied voltage non-selection state, a plurality of control voltage decoders, each of the control voltage decoders outputting a control voltage corresponding to either a control voltage selection state or a control voltage non-selection state and a plurality of driver circuits, each of the driver circuits being provided so as to correspond to each word line; receiving a first applied voltage, a second applied voltage and a control voltage which are output from a distinct combination of an applied voltage decoder and a control voltage decoder.
摘要翻译：根据本发明，提供了一种非易失性半导体存储装置，用于分别对每个字线施加与选择状态和非选择状态相对应的选择电压和非选择电压中的任一个。根据每个操作模式中的地址信号选择选择状态或非选择状态。非易失性半导体存储装置包括：根据施加的电压选择状态或施加的电压非选择状态操作的多个施加的电压解码器，多个控制电压解码器，每个控制电压解码器输出对应于控制电压选择状态或控制电压非选择状态以及多个驱动电路，每个驱动电路被设置为对应于每个字线; 接收从施加的电压解码器和控制电压解码器的不同组合输出的第一施加电压，第二施加电压和控制电压。

8. 发明授权

US06937520B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06937520B2
公开(公告)日：2005-08-30
申请号：US10760351
申请日：2004-01-21
申请人： Tsuyoshi Ono , Yasuaki Hirano , Masahiko Watanabe , Sau Ching Wong
发明人： Tsuyoshi Ono , Yasuaki Hirano , Masahiko Watanabe , Sau Ching Wong
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： In a nonvolatile floating-gate semiconductor memory device, a word line voltage supply circuit is configured to be able to apply gate voltages to the same memory cells such that the gate voltage applied at and after the second time is different from the gate voltage applied at the first time. At least one of the word line voltage supply circuit and the bit line voltage supply circuit is set to be able to apply a voltage to the same memory cells for a longer application period at the first time than at and after the second time. With this configuration, the threshold voltage distribution of the memory cells is controlled to be narrow.
摘要翻译：在非易失性浮栅半导体存储器件中，字线电压供给电路被配置为能够向相同的存储单元施加栅极电压，使得在第二时间施加的栅极电压与施加在第二时间的栅极电压不同第一次。字线电压供给电路和位线电压供给电路中的至少一个被设置为能够在第一时间比在第二时间和之后向相同存储器单元施加电压较长的施加周期。利用这种配置，将存储单元的阈值电压分布控制得很窄。

9. 发明授权

US06912161B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06912161B2
公开(公告)日：2005-06-28
申请号：US10611643
申请日：2003-07-02
申请人： Yasuaki Hirano , Yasumichi Mori , Shuichiro Kouchi
发明人： Yasuaki Hirano , Yasumichi Mori , Shuichiro Kouchi
IPC分类号： G11C16/04 , G11C11/56 , G11C16/06 , G11C16/10 , G11C16/28
CPC分类号： G11C11/5642 , G11C16/10 , G11C16/28 , G11C2211/5634
摘要： In the nonvolatile semiconductor memory device of this invention, a program control circuit 1 sets the threshold value of a first reference cell RFC0 by means of a write circuit WC on the basis of a result of comparing the threshold value of the first reference cell RFC0 with the threshold value of a second reference cell SRC executed by a sense amplifier 8 for trimming. The compare of threshold values by the sense amplifier 8 for trimming can be executed within a shorter time than in the threshold value read operation of the first reference cell RFC0. Therefore, when the number of the first reference cells is increased, the threshold value adjustment time can be remarkably reduced in comparison with the prior art in which the threshold value of the first reference cell is adjusted by reading the first reference cell.
摘要翻译：在本发明的非易失性半导体存储器件中，程序控制电路1基于比较第一参考单元RFC的阈值的结果，通过写入电路WC来设置第一参考单元RFC0的阈值 0与用于修整的读出放大器8执行的第二参考单元SRC的阈值。可以在比第一参考单元RFC 0的阈值读取操作更短的时间内执行用于修整的读出放大器8的阈值的比较。因此，当第一参考单元的数量增加时，阈值与通过读取第一参考单元来调整第一参考单元的阈值的现有技术相比，可以显着地减小调整时间。

10. 发明授权

US06711058B1 Erase method for nonvolatile semiconductor storage device and row decoder circuit for fulfilling the method 有权
标题翻译：用于实现该方法的非易失性半导体存储装置和行解码器电路的擦除方法
公开(公告)号：US06711058B1
公开(公告)日：2004-03-23
申请号：US09598384
申请日：2000-06-21
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C16/16 , G11C16/3418
摘要： For erasing a block 0, a voltage Vpp is applied to select word lines WL0-WL31, while a voltage Vneg is applied to each of the substrate (well) and sub-bit lines SBL0-SBL4096. Also, a voltage Vneg is applied to word lines WL32-WL63 of a non-select block 1, while the voltage Vneg is applied to the substrate (well) and the sub-bit lines SBL. Thus, the voltage Vneg is applied to the control gates, sources and drains of all the memory cells within the non-select block 1 and the substrate (well), so as to make them equal in voltage to one another. Therefore, there occur no mis-reads during the reading. Further, the capacity between the non-select word lines WL and the substrate (well) can be neglected, and the occupancy ratio of the charge pump for use of supply of the negative voltage can be reduced by an extent corresponding to 90% or more of the conventional counterpart. As a result, mis-reads due to substrate disturb during the erasing can be prevented.
摘要翻译：为了擦除块0，施加电压Vpp以选择字线WL0-WL31，同时将电压Vneg施加到每个衬底（阱）和子位线SBL0-SBL4096。此外，电压Vneg被施加到非选择块1的字线WL32-WL63，同时将电压Vneg施加到衬底（阱）和子位线SBL。因此，电压Vneg被施加到非选择块1和衬底（阱）内的所有存储单元的控制栅极，源极和漏极，以使得它们彼此之间的电压相等。因此，阅读期间不会发生误读。此外，可以忽略非选择字线WL和衬底（阱）之间的容量，并且可以将用于负电压的电源的电荷泵的占有率减小相当于90％以上的程度的传统对手。结果，可以防止在擦除期间由于衬底干扰而导致的误读。

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