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    • 4. 发明授权
    • Round-robin bus protocol
    • 循环总线协议
    • US07350002B2
    • 2008-03-25
    • US11008745
    • 2004-12-09
    • Yasser Ahmed
    • Yasser Ahmed
    • G06F13/00
    • G06F13/368
    • A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus passing control of the bus to the next device in the sequence. If the device has no data to transmit, the device simply places its address on the data lines, asserts the START signal, and asserts the END signal, and control passes directly to the next device in line. In this manner, each device has an opportunity to transmit on the bus.
    • 提供了包括一个或多个数据线和一个或多个控制线的低等待时间的对等TDM总线。 连接的设备按照总线地址顺序访问总线。 在设备访问期间,如果设备具有要发送的数据,则设备将其地址放置在数据线上,在总线上断言START信号,并继续向总线上的其他设备发送数据。 当数据传输完成时,器件在总线上断言END信号,从而将总线的控制按顺序传送到下一个器件。 如果设备没有要发送的数据,则设备只需将其地址放置在数据线上,断言START信号,并断言END信号,并且控制直接传递到下一个设备。 以这种方式,每个设备都有机会在总线上传输。
    • 5. 发明授权
    • Phase alignment between phase-skewed clock domains
    • 相位偏移时钟域之间的相位对准
    • US08699550B2
    • 2014-04-15
    • US13425467
    • 2012-03-21
    • Yasser AhmedXingdong Dai
    • Yasser AhmedXingdong Dai
    • H04B1/38H04L5/16
    • H04L7/02H04L7/0337
    • In order to compensate for phase offset between different sets of circuitry having different synchronous clock domains, transmit (TX) circuitry of one domain is configured to transmit a pattern signal (e.g., a pseudo random bit sequence) to receive (RX) circuitry of the other domain. The RX circuitry cycles through a number of different phase-shifted RX clock signals to determine which selected clock signals result in valid RX pattern signals. The RX circuitry is then able to select one of the phase-shifted clock signals for use in normal processing of an RX data signal received from the TX circuitry.
    • 为了补偿具有不同同步时钟域的不同电路组之间的相位偏移,一个域的发射(TX)电路被配置为发送模式信号(例如,伪随机位序列)以接收(RX)电路 其他域名 RX电路循环许多不同的相移RX时钟信号,以确定哪些选定的时钟信号产生有效的RX模式信号。 然后,RX电路能够选择一个相移时钟信号,以用于从TX电路接收的RX数据信号的正常处理。
    • 6. 发明申请
    • Methods and Apparatus for Detecting and Decoding Adaptive Equalization Training Frames
    • 用于检测和解码自适应均衡训练帧的方法和装置
    • US20090168862A1
    • 2009-07-02
    • US11967463
    • 2007-12-31
    • Yasser AhmedXingdong DaiMohammad S. MobinLane A. Smith
    • Yasser AhmedXingdong DaiMohammad S. MobinLane A. Smith
    • H04L27/01
    • H04L27/01H04L7/0066H04L7/0083H04L25/4904
    • Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.
    • 提供了用于检测和解码自适应均衡训练帧(具有包括二进制和二进制零序列的帧标记)的方法和装置。 通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时,检测所述帧标记。 使用框架制造商的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。
    • 7. 发明申请
    • Round-Robin Bus Protocol
    • 轮回总线协议
    • US20080126640A1
    • 2008-05-29
    • US12025462
    • 2008-02-04
    • Yasser Ahmed
    • Yasser Ahmed
    • G06F13/00
    • G06F13/368
    • A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus passing control of the bus to the next device in the sequence. If the device has no data to transmit, the device simply places its address on the data lines, asserts the START signal, and asserts the END signal, and control passes directly to the next device in line. In this manner, each device has an opportunity to transmit on the bus.
    • 提供了包括一个或多个数据线和一个或多个控制线的低等待时间的对等TDM总线。 连接的设备按照总线地址顺序访问总线。 在设备访问期间,如果设备具有要发送的数据,则设备将其地址放置在数据线上,在总线上断言START信号,并继续向总线上的其他设备发送数据。 当数据传输完成时,器件在总线上断言END信号,从而将总线的控制按顺序传送到下一个器件。 如果设备没有要发送的数据,则设备只需将其地址放置在数据线上,断言START信号,并断言END信号,并且控制直接传递到下一个设备。 以这种方式,每个设备都有机会在总线上传输。