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1. 发明授权

US4439697A Sense amplifier circuit 失效
标题翻译：感应放大电路
公开(公告)号：US4439697A
公开(公告)日：1984-03-27
申请号：US333321
申请日：1981-12-22
申请人： Yasoji Suzuki , Hiroaki Suzuki , Yukihiro Saeki
发明人： Yasoji Suzuki , Hiroaki Suzuki , Yukihiro Saeki
IPC分类号： G11C17/00 , G11C11/419 , G11C17/12 , G11C17/18 , H03K5/153 , G11C7/06 , H03K5/24
CPC分类号： G11C17/12
摘要： A sense amplifier circuit is disclosed in which a ROM is grouped into a plurality of ROM arrays and outputs from sense amplifiers provided for each ROM array are supplied to a single output terminal. In the sense amplifier circuit, each sense amplifier has a P-MOS FET connected between the output of the ROM array and a ground terminal and connected at the gate to a preset terminal, P-MOS FETs connected between the output of the ROM array and a positive power source and whose gates are respectively connected to the output terminal and a preset terminal, and an N MOS FET connected between the output terminal and the ground terminal and at the gate to the output terminal of the ROM array. Further, a P MOS FET is connected between the output terminal and the power source terminal and at the gate to an inverted preset terminal.
摘要翻译：公开了一种读出放大器电路，其中ROM被分组成多个ROM阵列，并且为每个ROM阵列提供的读出放大器的输出被提供给单个输出端。在感测放大器电路中，每个读出放大器具有连接在ROM阵列的输出端和接地端子之间的P-MOS FET，并且在门极连接到预置端子，连接在ROM阵列的输出端和正电源，其栅极分别连接到输出端子和预置端子，以及连接在输出端子和接地端子之间以及连接到ROM阵列的输出端子的栅极的N MOS FET。此外，P MOS FET连接在输出端子和电源端子之间，并且在栅极处连接到反相的预置端子。

2. 发明授权

US06046626A Voltage transfer circuit and a booster circuit, and an IC card comprising the same 失效
标题翻译：电压传输电路和升压电路，以及包括该电路的IC卡
公开(公告)号：US06046626A
公开(公告)日：2000-04-04
申请号：US3946
申请日：1998-01-08
申请人： Yukihiro Saeki , Yasoji Suzuki
发明人： Yukihiro Saeki , Yasoji Suzuki
IPC分类号： G11C11/413 , G06K19/07 , G11C11/407 , G11C16/06 , H02M3/07 , H03K19/0948 , G05F3/02
CPC分类号： H02M3/073
摘要： A voltage transfer circuit comprises a first MOS transistor of a first channel type having a drain terminal connected to a first node supplied with a predetermined voltage, a source terminal connected to a second node, and a gate terminal, a second MOS transistor of a first channel type having a source terminal connected to the second node, a drain terminal connected to the gate terminal of the first MOS transistor, and a gate terminal supplied with a clock signal, as well as a third MOS transistor of a second channel type having a drain terminal connected to the drain terminal of the second MOS transistor, a source terminal connected to a third node supplied with a reference voltage, and a gate terminal supplied with the clock signal.
摘要翻译：电压传输电路包括第一通道类型的第一MOS晶体管，其具有连接到被提供有预定电压的第一节点的漏极端子，连接到第二节点的源极端子和栅极端子，第一MOS晶体管的第一沟道型，具有连接到第二节点的源极端子，连接到第一MOS晶体管的栅极端子的漏极端子和提供有时钟信号的栅极端子，以及具有第二沟道类型的第三MOS晶体管，其具有漏极端子连接到第二MOS晶体管的漏极端子，连接到提供有参考电压的第三节点的源极端子和被提供有时钟信号的栅极端子。

3. 发明授权

US4404663A Integrated circuit 失效
标题翻译：集成电路
公开(公告)号：US4404663A
公开(公告)日：1983-09-13
申请号：US234438
申请日：1981-02-13
申请人： Yukihiro Saeki , Fuminari Tanaka , Yasoji Suzuki
发明人： Yukihiro Saeki , Fuminari Tanaka , Yasoji Suzuki
IPC分类号： G06F1/18 , G06F3/00 , G11C5/06 , G11C7/10 , G11C7/00
CPC分类号： G11C5/063 , G11C7/10 , G11C7/1006
摘要： An integrated circuit wherein a gate circuit is provided on a bus line mounted on a semiconductor substrate. The gate circuit is used to separate an unused circuit block from other circuit blocks which are connected to a bus line through an input-output circuit for high speed data transmission, thereby reducing a parasitic capacity which might be imparted to the bus line by the separated circuit block. The input-output circuit is formed of a clocked inverter. The gate circuit is formed of a C.multidot.MOS transmission gate. The input-output circuit and gate circuit are so connected that where the gate of the inverter is opened, then the C.multidot.MOS transmission gate is closed; and where the gate of the inverter is closed, then the C.multidot.MOS transmission gate is opened.
摘要翻译：一种集成电路，其中门电路设置在安装在半导体衬底上的总线上。门电路用于将未使用的电路块与通过用于高速数据传输的输入 - 输出电路连接到总线的其它电路块分离，从而减少可能通过分离的总线赋予总线的寄生电容电路块。输入输出电路由时钟反相器构成。门电路由CxMOS传输门形成。输入输出电路和门电路如此连接，使逆变器的门打开，则CxMOS传输门关闭; 并且逆变器的门关闭，则CxMOS传输门打开。

4. 发明授权

US5027012A Programmable logic circuit using wired-or tristate gates 失效
标题翻译：使用有线或三态门的可编程逻辑电路
公开(公告)号：US5027012A
公开(公告)日：1991-06-25
申请号：US480898
申请日：1990-02-16
申请人： Yukihiro Saeki , Yasoji Suzuki
发明人： Yukihiro Saeki , Yasoji Suzuki
IPC分类号： H03K19/20 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17704 , H03K19/1731
摘要： A programmable logic circuit for deriving a logic output of first and second signals includes a 2-input logic gate for deriving a logic output of two signals. The 2-input logic gate is constituted by connecting two 3-state circuits in a wired OR configuration. One of the 3-state circuits includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives an inverted signal of the second signal, and the data output terminal is set to one of three states of "1", "0", and the high impedance. Likewise, the other 3-state circuit includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives the second signal, and the data output terminal is set to one of three states of "1", "0", and the high impedance. Each of the data input terminals of the 3-state circuits is supplied with a desired one of the first signal, an inverted signal of the first signal, a "0" level signal, and a "1" level signal in a programmable fashion. Various logic gates can be realized by programming the supplying states of the four signals.

5. 发明授权

US07167016B2 Operation mode setting circuit 有权
标题翻译：工作模式设定电路
公开(公告)号：US07167016B2
公开(公告)日：2007-01-23
申请号：US11062796
申请日：2005-02-23
申请人： Yukihiro Saeki
发明人： Yukihiro Saeki
IPC分类号： H03K19/00
CPC分类号： G01R31/31701
摘要： According to the present invention, there is provided an operation mode setting circuit comprising: a plurality of latch circuits each of which receives one of at least two bits contained in an operation mode setting signal for setting an operation mode, and latches and outputs the bit in synchronism with a clock; an inverter which inverts at least one of output signals from said latch circuits; and a logic circuit which receives the output signals from said latch circuits and the signal inverted by said inverter, performs a predetermined logic operation, and outputs a result.
摘要翻译：根据本发明，提供了一种操作模式设置电路，包括：多个锁存电路，每个锁存电路接收包含在用于设置操作模式的操作模式设置信号中的至少两个位中的一个，并锁存并输出该位与时钟同步; 反相器，其将来自所述锁存电路的输出信号中的至少一个反相; 以及逻辑电路，其接收来自所述锁存电路的输出信号和由所述反相器反相的信号，执行预定的逻辑运算，并输出结果。

6. 发明授权

US4486753A Bus line drive circuit 失效
标题翻译：总线驱动电路
公开(公告)号：US4486753A
公开(公告)日：1984-12-04
申请号：US398892
申请日：1982-07-16
申请人： Yukihiro Saeki , Kazuyuki Uchida
发明人： Yukihiro Saeki , Kazuyuki Uchida
IPC分类号： G06F3/00 , G06F13/40 , H03K19/0185 , H04L25/02 , H04Q9/00 , H03K5/08
CPC分类号： G06F13/4077 , H03K19/018557
摘要： A bus line drive circuit comprising a bus line allowing data to transfer therethrough, a precharge circuit connected to the bus line for precharging the bus line with precharge pulse, input/output circuit connected to the bus line for transferring data to and from an ALU through the bus line, and positive feedback circuit connected to the bus line, which exhibits a high impedance during a precharge period to electrically be disconnected from the bus line, keeps a precharge potential when the potential on the bus line is equal to the precharge potential during an active period, and expands a potential difference when the potential on the bus line is slightly different from the precharge potential.
摘要翻译：一种总线驱动电路，包括允许数据传输的总线线路，连接到总线的预充电电路，用于预充电脉冲的总线线路，连接到总线的输入/输出电路，用于将数据传送到ALU或从ALU传送数据总线线路和连接到总线的正反馈电路在预充电期间呈现高阻抗以与母线断开以在母线上的电位等于预充电电位时保持预充电电位并且当总线上的电位略微不同于预充电势时，扩展电位差。

7. 发明授权

US6068430A Mounting mechanism for a pin mirror cutter 有权
标题翻译：针镜切割机的安装机构
公开(公告)号：US6068430A
公开(公告)日：2000-05-30
申请号：US235312
申请日：1999-01-22
申请人： Yukihiro Saeki , Syoji Takiguchi , Nobukazu Horiike
发明人： Yukihiro Saeki , Syoji Takiguchi , Nobukazu Horiike
IPC分类号： B23C5/22 , B23C5/20
CPC分类号： B23C5/26 , B23C5/2234 , B23C2210/503 , B23C2220/68 , Y10T407/15 , Y10T407/191 , Y10T407/1926 , Y10T407/1956 , Y10T82/19 , Y10T82/192 , Y10T82/2527
摘要： In a mounting mechanism for a pin mirror cutter 22, the cutter body 22 is mounted with its outer periphery inserted into the inner periphery of a cutter mounting portion. an inclined surface of a tapered portion 22 formed on the cutter body and an inclined surface of a tapered portion formed on the cutter mounting portion are in surface-contact with each other, and the diameters of the contact surfaces gradually decrease in the direction of insertion of the cutter body into the cutter mounting portion. Furthermore, these inclined surfaces and are formed by a plurality of flat surfaces so as to form regular octagonal pyramid surfaces.
摘要翻译：在针镜切割器22的安装机构中，刀体22被安装成其外周插入刀具安装部的内周。形成在刀体上的锥形部分22的倾斜表面和形成在刀具安装部分上的锥形部分的倾斜表面彼此表面接触，并且接触表面的直径在插入方向上逐渐减小的切割器本体进入切割器安装部分。此外，这些倾斜面由多个平面形成，形成规则的八角锥面。

8. 发明授权

US5229972A Nonvolatile semiconductor memory system 失效
标题翻译：非易失性半导体存储器系统
公开(公告)号：US5229972A
公开(公告)日：1993-07-20
申请号：US639331
申请日：1991-01-10
申请人： Hitoshi Kondo , Tetsuya Yamamoto , Yukihiro Saeki
发明人： Hitoshi Kondo , Tetsuya Yamamoto , Yukihiro Saeki
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C16/34
CPC分类号： G11C16/105 , G11C16/102 , G11C16/34
摘要： An EPROM integrated circuit includes a plurality of banks. When a data write operation is to be performed for this EEPROM integrated circuit, a bank which is used once is not used again, but the operation is constantly performed for new banks. In order to select a bank, a write number storage area is provided in the EPROM integrated circuit, and the contents of the write number storage area are updated by a write number updating circuit each time the write operation is performed for a new bank.

9. 发明授权

US5050124A Semiconductor memory having load transistor circuit 失效
标题翻译：具有负载晶体管的半导体存储器
公开(公告)号：US5050124A
公开(公告)日：1991-09-17
申请号：US94706
申请日：1987-09-09
申请人： Yukihiro Saeki , Toshimasa Nakamura
发明人： Yukihiro Saeki , Toshimasa Nakamura
IPC分类号： G11C16/04
CPC分类号： G11C16/0416
摘要： A p-channel MOS transistor is connected in series to a floating gate n-channel MOS transistor forming a memory cell, so that the p-channel MOS transistor functions as the load of the memory cell. The operational characteristic of the p-channel MOS transistor determines the data-writing current of the memory cell. Hence, hardly any change occurs in the data-writing current, even if the operation characteristic of the memory cell changes. A semiconductor memory includes memory cells constituted by floating gate n-channel MOS transistors. The memory further includes a data-reading, column-selecting circuit comprising n-channel MOS transistors, and a data-writing, column-selecting circuit comprising p-channel MOS transistors. By way of the above structure, the data-writing voltage can be prevented from being lowered.

10. 发明授权

US4932389A Slicing apparatus with work-feeding mechanism in feedback control 失效
标题翻译：具有反馈控制工作进给机构的切片机
公开(公告)号：US4932389A
公开(公告)日：1990-06-12
申请号：US260200
申请日：1988-10-20
申请人： Yukihiro Saeki , Masatoshi Tagami
发明人： Yukihiro Saeki , Masatoshi Tagami
IPC分类号： B23Q5/26 , B28D1/22 , B28D5/00 , B28D5/02 , B28D7/00
CPC分类号： B28D5/028 , B28D5/0064 , B28D5/024
摘要： A slicing apparatus includes: an annular plate-like rotary blade adapted to be rotated about an axle thereof and having an inner peripheral cutting edge; a table for carrying a work; a first work-feeding mechanism for moving the work on the table in a direction parallel to the axis of the rotary blade; and a second work-feeding mechanism for moving the table in a direction parallel to the opposite side of the blade so as to cause the work on the table to be sliced by the blade. The second work feeding mechanism includes: a hydraulic cylinder operatively connected to the table; a pressure oil-supplying mechanism for supplying the hydraulic cylinder with a pressure oil; a rotary valve for controlling the flow rate of the pressure oil to be supplied to the hydraulic cylinder, the rotary valve having a rotary input shaft of which rotational position determines the flow rate of the pressure oil passing through the rotary valve; a drive mechanism for rotating the input shaft of the rotary valve; a cutting speed sensor for substantially detecting the travel speed of the table which is moved by the hydraulic cylinder and for outputting a feedback signal; and a control unit for controlling the drive mechanism according to the feedback signal outputted by the speed sensor so that the actual travel speed of the table is equal to a predetermined travel speed for the table.
摘要翻译：切片装置包括：环形板状旋转刀片，其适于绕其轴线旋转并具有内周切削刃; 一张载着工作的桌子; 第一加工机构，用于沿与所述旋转叶片的轴线平行的方向在所述工作台上移动所述工件; 以及第二加工机构，用于沿着平行于叶片的相对侧的方向移动工作台，以便使刀片上的工件被切割。第二工作进给机构包括：可操作地连接到工作台的液压缸; 用于向液压缸供给压力油的压力供油机构; 用于控制供给到液压缸的压力油的流量的旋转阀，旋转阀具有旋转输入轴，旋转位置决定了通过旋转阀的压力油的流量; 用于旋转所述旋转阀的输入轴的驱动机构; 切割速度传感器，用于基本上检测由液压缸移动的工作台的行进速度并输出反馈信号; 以及控制单元，用于根据由速度传感器输出的反馈信号来控制驱动机构，使得工作台的实际行驶速度等于工作台的预定行驶速度。

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