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1. 发明授权

US4264968A Basic circuit for electronic timepieces 失效
标题翻译：电子钟表基本电路
公开(公告)号：US4264968A
公开(公告)日：1981-04-28
申请号：US864714
申请日：1977-12-27
申请人： Yasoji Suzuki , Fuminari Tanaka , Yasushi Sato
发明人： Yasoji Suzuki , Fuminari Tanaka , Yasushi Sato
IPC分类号： G01R19/00 , G04G3/02 , G04G9/00 , G04G99/00 , G04C3/00
CPC分类号： G04G99/00 , G04G3/022
摘要： There is provided an electronic timepiece basic circuit comprising a pulse generating circuit for generating 1 Hz pulses, a first terminal group having a plurality of terminals including a terminal connected to the output terminal of the pulse generating circuit, a second terminal group having terminals to be connected to the terminals of the first terminal group, respectively, 10 scale counters coupled with the second terminal group, 6 scale counters connected to the 10 scale counters, a display unit, and a decoder which is coupled with the 10 scale counters and the 6 scale counters and decodes the contents of the 10 and 6 scale counters and delivers the decoded contents to the display unit. The first and second terminal groups are properly coupled to each other. The combination of the 10 scale counters and the 6 scale counters is properly modified so as to form a 12, 24, or 60 scale counter, as necessary.
摘要翻译：提供了一种电子钟表基本电路，包括用于产生1Hz脉冲的脉冲发生电路，具有包括连接到脉冲发生电路的输出端的端子的多个端子的第一端子组，具有端子的第二端子组分别连接到第一终端组的终端，与第二终端组耦合的10个比例计数器，连接到10个比例计数器的6个比例计数器，显示单元和与10个比例计数器耦合的解码器，6 缩放计数器并解码10和6比例计数器的内容，并将解码的内容传送到显示单元。第一和第二端子组彼此适当地联接。 10个刻度计数器和6个刻度计数器的组合被适当修改，以便根据需要形成12个，24个或60个刻度计数器。

2. 发明授权

US4404663A Integrated circuit 失效
标题翻译：集成电路
公开(公告)号：US4404663A
公开(公告)日：1983-09-13
申请号：US234438
申请日：1981-02-13
申请人： Yukihiro Saeki , Fuminari Tanaka , Yasoji Suzuki
发明人： Yukihiro Saeki , Fuminari Tanaka , Yasoji Suzuki
IPC分类号： G06F1/18 , G06F3/00 , G11C5/06 , G11C7/10 , G11C7/00
CPC分类号： G11C5/063 , G11C7/10 , G11C7/1006
摘要： An integrated circuit wherein a gate circuit is provided on a bus line mounted on a semiconductor substrate. The gate circuit is used to separate an unused circuit block from other circuit blocks which are connected to a bus line through an input-output circuit for high speed data transmission, thereby reducing a parasitic capacity which might be imparted to the bus line by the separated circuit block. The input-output circuit is formed of a clocked inverter. The gate circuit is formed of a C.multidot.MOS transmission gate. The input-output circuit and gate circuit are so connected that where the gate of the inverter is opened, then the C.multidot.MOS transmission gate is closed; and where the gate of the inverter is closed, then the C.multidot.MOS transmission gate is opened.
摘要翻译：一种集成电路，其中门电路设置在安装在半导体衬底上的总线上。门电路用于将未使用的电路块与通过用于高速数据传输的输入 - 输出电路连接到总线的其它电路块分离，从而减少可能通过分离的总线赋予总线的寄生电容电路块。输入输出电路由时钟反相器构成。门电路由CxMOS传输门形成。输入输出电路和门电路如此连接，使逆变器的门打开，则CxMOS传输门关闭; 并且逆变器的门关闭，则CxMOS传输门打开。

3. 发明授权

US06046626A Voltage transfer circuit and a booster circuit, and an IC card comprising the same 失效
标题翻译：电压传输电路和升压电路，以及包括该电路的IC卡
公开(公告)号：US06046626A
公开(公告)日：2000-04-04
申请号：US3946
申请日：1998-01-08
申请人： Yukihiro Saeki , Yasoji Suzuki
发明人： Yukihiro Saeki , Yasoji Suzuki
IPC分类号： G11C11/413 , G06K19/07 , G11C11/407 , G11C16/06 , H02M3/07 , H03K19/0948 , G05F3/02
CPC分类号： H02M3/073
摘要： A voltage transfer circuit comprises a first MOS transistor of a first channel type having a drain terminal connected to a first node supplied with a predetermined voltage, a source terminal connected to a second node, and a gate terminal, a second MOS transistor of a first channel type having a source terminal connected to the second node, a drain terminal connected to the gate terminal of the first MOS transistor, and a gate terminal supplied with a clock signal, as well as a third MOS transistor of a second channel type having a drain terminal connected to the drain terminal of the second MOS transistor, a source terminal connected to a third node supplied with a reference voltage, and a gate terminal supplied with the clock signal.
摘要翻译：电压传输电路包括第一通道类型的第一MOS晶体管，其具有连接到被提供有预定电压的第一节点的漏极端子，连接到第二节点的源极端子和栅极端子，第一MOS晶体管的第一沟道型，具有连接到第二节点的源极端子，连接到第一MOS晶体管的栅极端子的漏极端子和提供有时钟信号的栅极端子，以及具有第二沟道类型的第三MOS晶体管，其具有漏极端子连接到第二MOS晶体管的漏极端子，连接到提供有参考电压的第三节点的源极端子和被提供有时钟信号的栅极端子。

4. 发明授权

US6020869A Multi-gray level display apparatus and method of displaying an image at many gray levels 失效
公开(公告)号：US6020869A
公开(公告)日：2000-02-01
申请号：US841389
申请日：1997-04-30
申请人： Itsuo Sasaki , Yasoji Suzuki , Hirofumi Kato , Isao Arita , Toshio Yanagisawa , Kazuyoshi Yamamoto , Hiroyoshi Murata , Hiroyuki Hamagawa
发明人： Itsuo Sasaki , Yasoji Suzuki , Hirofumi Kato , Isao Arita , Toshio Yanagisawa , Kazuyoshi Yamamoto , Hiroyoshi Murata , Hiroyuki Hamagawa
IPC分类号： G09G3/20 , G09G3/36 , G09G3/28 , G09G3/30 , G09G5/10
CPC分类号： G09G3/3648 , G09G2310/027 , G09G3/2007 , G09G3/2018
摘要： A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

5. 发明授权

US4558234A Complementary MOSFET logic circuit 失效
标题翻译：互补MOSFET逻辑电路
公开(公告)号：US4558234A
公开(公告)日：1985-12-10
申请号：US652429
申请日：1984-09-20
申请人： Yasoji Suzuki , Kenji Matsuo
发明人： Yasoji Suzuki , Kenji Matsuo
IPC分类号： H03K19/017 , H03K19/0175 , H03K19/0944 , H03K19/092 , H03K19/003 , H03K19/01 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/01721 , H03K19/017518
摘要： Disclosed is a complementary MOSFET logic circuit having a complementary MOS inverter with a pregiven ratio of the channel widths of a P channel MOSFET and an N channel MOSFET and pregiven threshold voltages of the FETs so as to have an input voltage characteristic adapted to an output voltage characteristic, and a buffer circuit which includes a bipolar transistor for receiving at the base thereof a signal from the output terminal of the complementary MOS inverter and an N channel MOSFET for receiving at the gate thereof an input signal applied to the complementary MOS inverter. The inverter and buffer are connected in series to one another between a high potential applying point and a low potential applying point, and a signal corresponding to a logic output signal of the complementary MOS inverter is produced at the output terminal thereof.
摘要翻译：公开了具有互补MOS反相器的互补MOSFET逻辑电路，其具有P沟道MOSFET和N沟道MOSFET的沟道宽度的预制比和FET的预定阈值电压，以便具有适于输出电压的输入电压特性特性和缓冲电路，其包括用于在其基极处接收来自互补MOS反相器的输出端的信号的双极晶体管和用于在其栅极处接收施加到互补MOS反相器的输入信号的N沟道MOSFET。反相器和缓冲器在高电位施加点和低电位施加点之间彼此串联连接，并且在其输出端产生与互补MOS反相器的逻辑输出信号相对应的信号。

6. 发明授权

US4546327A Analog signal power amplifier circuit 失效
标题翻译：模拟信号功率放大器电路
公开(公告)号：US4546327A
公开(公告)日：1985-10-08
申请号：US513308
申请日：1983-07-13
申请人： Yasoji Suzuki , Itsuo Sasaki , Shouji Abou
发明人： Yasoji Suzuki , Itsuo Sasaki , Shouji Abou
IPC分类号： H03F3/20 , H03F3/213 , H03F3/45 , H03F3/72
CPC分类号： H03F3/213 , H03F3/45183 , H03F3/72 , H03F2200/03 , H03F2200/507 , H03F2200/522 , H03F2203/45508 , H03F2203/45674
摘要： A signal corresponding to an analog input signal is supplied to one of two input terminals of a two-input, one-output MOS differential amplifier. A reference voltage signal is supplied to the other of the two input terminals of the MOS differential amplifier. A bipolar transistor having one end connected to an analog signal output terminal is driven by a signal from the output terminal of the MOS differential amplifier. A loudspeaker is driven by the bipolar transistor.
摘要翻译：对应于模拟输入信号的信号被提供给双输入一输出MOS差分放大器的两个输入端中的一个。将参考电压信号提供给MOS差分放大器的两个输入端子中的另一个。具有连接到模拟信号输出端的一端的双极晶体管由来自MOS差分放大器的输出端的信号驱动。扬声器由双极晶体管驱动。

7. 发明授权

US4280272A Method for preparing complementary semiconductor device 失效
标题翻译：互补半导体器件的制备方法
公开(公告)号：US4280272A
公开(公告)日：1981-07-28
申请号：US85595
申请日：1979-10-17
申请人： Hideharu Egawa , Koji Matsuki , Yasoji Suzuki
发明人： Hideharu Egawa , Koji Matsuki , Yasoji Suzuki
IPC分类号： H01L21/8238 , H01L21/8247 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/22 , H01L21/265
CPC分类号： H01L21/823807 , H01L27/0928
摘要： A complementary semiconductor device includes P-and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.
摘要翻译：互补半导体器件包括分别形成在半导体衬底中并具有基本相同的杂质浓度的P型和N型半导体区域。 N沟道型和P沟道型硅栅极场效应晶体管分别形成在P沟道型和N沟道型区域中。 P型和N沟道型硅栅场效应晶体管的栅电极由相同导电类型的多晶硅形成。相同导电类型的杂质被掺杂到两个半导体区域中以提供沟道掺杂区域。

8. 发明授权

US4255678A Voltage sense circuit 失效
标题翻译：电压检测电路
公开(公告)号：US4255678A
公开(公告)日：1981-03-10
申请号：US962221
申请日：1978-11-20
申请人： Yasoji Suzuki , Kiyofumi Ochii , Hirozi Asahi
发明人： Yasoji Suzuki , Kiyofumi Ochii , Hirozi Asahi
IPC分类号： G11C11/41 , G11C11/409 , G11C11/419 , H03K5/24 , G11C7/00
CPC分类号： G11C11/419
摘要： A voltage sense circuit in which first and second parallel connections of complementary MOS transistors are connected between a pair of signal lines connected to memory cells and outputs of a flip-flop circuit for detecting a potential change of the signal line caused by data readout from an accessed memory cell. MOS transistors of one channel type in the parallel connections are adapted to precharge output node capacitors of the flip-flop circuit to a supply voltage level, while MOS transistors of the other channel type are adapted to couple complementary output voltage levels of the flip-flop circuit produced after the data readout and operation of the flip-flop circuit to the signal lines. Use of the parallel connections of complementary MOS transistors enables the application of a single power source for producing gate signals of these MOS transistors.
摘要翻译：一种电压检测电路，其中互补MOS晶体管的第一和第二并联连接在连接到存储单元的一对信号线之间，并且用于检测由数据读出引起的信号线的电位变化的触发器电路的输出存取存储单元并联连接中的一个通道类型的MOS晶体管适于将触发器电路的输出节点电容器预充电到电源电压电平，而另一个通道类型的MOS晶体管适于耦合触发器的互补输出电压电平在触发电路的数据读出和操作到信号线之后产生的电路。使用互补MOS晶体管的并联连接使得能够应用单个电源来产生这些MOS晶体管的栅极信号。

9. 发明授权

US4044342A Dynamic type semiconductor memory device 失效
标题翻译：动态型半导体存储器件
公开(公告)号：US4044342A
公开(公告)日：1977-08-23
申请号：US679177
申请日：1976-04-22
申请人： Yasoji Suzuki , Kiyofumi Ochii
发明人： Yasoji Suzuki , Kiyofumi Ochii
IPC分类号： G11C11/405 , G11C11/406 , G11C11/40
CPC分类号： G11C11/406 , G11C11/405
摘要： The dynamic type semiconductor memory device comprises a refresh circuit and a plurality of memory cells which are connected between a data input line and a data output line, a plurality of read/write command signal lines and a plurality of word selection lines provided for respective semiconductor memory cells. Each semiconductor memory cell comprises serially connected first p-channel MOS transistor and a second n-channel MOS transistor having gate electrodes connected to the read/write command signal line and the data input line respectively, a third p-channel MOS transistor connected between the data output line and the word selection line and having a gate electrode connected to the node between the first and second transistors, and a parasitic capacitance connected to the node between the first and second transistors for storing data.
摘要翻译：动态型半导体存储器件包括一个连接在数据输入线和数据输出线之间的刷新电路和多个存储器单元，多个读/写命令信号线和为各个半导体提供的多个字选择线记忆细胞每个半导体存储单元包括串联连接的第一p沟道MOS晶体管和第二n沟道MOS晶体管，第二n沟道MOS晶体管分别具有连接到读取/写入命令信号线和数据输入线的栅电极，第三p沟道MOS晶体管连接在数据输出线和字选择线，并且具有连接到第一和第二晶体管之间的节点的栅电极，以及连接到用于存储数据的第一和第二晶体管之间的节点的寄生电容。

10. 发明授权

US3992635A N scale counter 失效
标题翻译： N比例计数器
公开(公告)号：US3992635A
公开(公告)日：1976-11-16
申请号：US632575
申请日：1975-11-17
申请人： Yasoji Suzuki , Kenshi Manabe , Teruaki Tanaka , Tomohisa Shigematsu
发明人： Yasoji Suzuki , Kenshi Manabe , Teruaki Tanaka , Tomohisa Shigematsu
IPC分类号： H03K23/52 , H03K21/02 , H03K23/54 , H03K23/30
CPC分类号： H03K21/02
摘要： An n scale counter includes a shift register having X number of unit delay circuits connected in series and each consisting of a plurality of insulated gate field effect transistors. The unit delay circuits of the shift register are simultaneously supplied with pulses to be counted and each of the delay cicuits is set or reset to an initial state. There is also provided a closed loop circuit including a first gate circuit connected to receive an output signal from the last stage delay circuit as one input terminal, and a logic circuit connected to receive output signals from the first gate circuit and, for example, the first stage delay circuit and produce to the input terminal of the first stage delay circuit an output signal indicating coincidence or incoincidence of its input signals. The counter is capable of counting pulses of (2.sup.x -1) at maximum. A second gate circuit is provided to apply its output signal to the other input terminal of the first gate circuit and output signals of a predetermined combination from the unit delay circuits are supplied to the second gate circuit so that the counter can function as a counter with a counting capacity smaller than that of (2.sup.x -1).
摘要翻译： n比例计数器包括具有X个单元延迟电路的移位寄存器，它们串联连接，并且每个由多个绝缘栅场效应晶体管组成。移位寄存器的单位延迟电路同时提供要计数的脉冲，并且每个延迟电路被设置或复位到初始状态。还提供了一种闭环电路，包括连接成将来自最后级延迟电路的输出信号作为一个输入端子接收的第一门电路和连接成接收来自第一门电路的输出信号的逻辑电路，例如，第一级延迟电路，并向第一级延迟电路的输入端产生指示其输入信号一致或不一致的输出信号。计数器最多能够计数（2x-1）的脉冲。提供第二门电路以将其输出信号施加到第一门电路的另一输入端，并且将来自单元延迟电路的预定组合的输出信号提供给第二门电路，使得计数器可用作具有计数容量小于（2x-1）的计数容量。

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