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1. 发明申请

US20100167512A1 Methods for Nanostructure Doping 审中-公开
标题翻译：纳米结构掺杂方法
公开(公告)号：US20100167512A1
公开(公告)日：2010-07-01
申请号：US12720125
申请日：2010-03-09
申请人： Yaoling Pan , Jian Chen , Francisco Leon , Shahriar Mostarshed , Linda T. Romano , Vijendra Sahi , David P. Stumbo
发明人： Yaoling Pan , Jian Chen , Francisco Leon , Shahriar Mostarshed , Linda T. Romano , Vijendra Sahi , David P. Stumbo
IPC分类号： H01L21/22
CPC分类号： H01L29/0665 , B81C1/00698 , B81C2201/0173 , B82Y10/00 , H01L21/2256 , H01L21/268 , H01L29/0673
摘要： Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.
摘要翻译：公开了掺杂纳米结构的方法，例如纳米线。该方法提供了改进现有掺杂纳米结构方法的各种方法。这些实施方案包括在后纳米结构合成掺杂期间使用牺牲层来促进纳米结构内的均匀掺杂剂分布。在另一个实施例中，当使用高能离子注入时，使用高温环境退火纳米结构损伤。在另一个实施方案中，使用快速热退火来将掺杂剂从纳米结构上的掺杂剂层驱动到纳米结构中。在另一个实施例中，提供了一种在塑料衬底上掺杂纳米线的方法，其包括在塑料衬底上沉积电介质叠层以保护塑料衬底免于在掺杂过程期间损坏。还提供了一种实施方案，其包括在合成纳米结构中在不同时间选择性地使用高浓度的掺杂剂材料以在所得纳米结构内实现新的晶体结构。

2. 发明授权

US07951422B2 Methods for oriented growth of nanowires on patterned substrates 有权
标题翻译：在图案化衬底上纳米线定向生长的方法
公开(公告)号：US07951422B2
公开(公告)日：2011-05-31
申请号：US11641939
申请日：2006-12-20
申请人： Yaoling Pan , Xiangfeng Duan , Robert S. Dubrow , Jay Goldman , Shahriar Mostarshed , Chunming Niu , Linda T. Romano , David P. Stumbo , Alice Fischer-Colbrie , Vijendra Sahi , Virginia Robbins
发明人： Yaoling Pan , Xiangfeng Duan , Robert S. Dubrow , Jay Goldman , Shahriar Mostarshed , Chunming Niu , Linda T. Romano , David P. Stumbo , Alice Fischer-Colbrie , Vijendra Sahi , Virginia Robbins
IPC分类号： C23C16/00
CPC分类号： C30B29/605 , B82Y30/00 , C30B11/12 , C30B29/06 , Y10T428/24917
摘要： The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors, as well as us of patterned substrates to grow oriented nanowires. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.
摘要翻译：本发明涉及用于纳米线生长和收获的系统和方法。在一个实施例中，提供了用于纳米线生长和掺杂的方法，包括使用硅前体的组合的外延取向纳米线生长的方法，以及我们用于生长取向的纳米线的图案化衬底。在本发明的另一方面，提供了通过使用牺牲生长层来提高纳米线质量的方法。在本发明的另一方面，提供了将纳米线从一个衬底转移到另一个衬底的方法。

3. 发明申请

US20090050974A1 Method, System and Apparatus for Gating Configurations and Improved Contacts in Nanowire-Based Electronic Devices 失效
标题翻译：基于纳米线的电子设备中门控配置和改进接点的方法，系统和设备
公开(公告)号：US20090050974A1
公开(公告)日：2009-02-26
申请号：US12244573
申请日：2008-10-02
申请人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
发明人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
IPC分类号： H01L47/00 , H01L21/8234
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L29/785 , H01L29/78645 , H01L29/78681 , H01L29/7869 , Y10S977/762 , Y10S977/932 , Y10S977/938
摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
摘要翻译：描述了具有改进的门结构的电子设备的方法，系统和装置。电子装置包括至少一个纳米线。栅极接触沿至少一个纳米线的长度的至少一部分定位。介电材料层在栅极接触和至少一个纳米线之间。源极触点和漏极触点与至少一个纳米线接触。源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。环形第一栅极区域沿着纳米线长度的一部分包围纳米线。第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

4. 发明申请

US20100144103A1 Method, System and Apparatus for Gating Configurations and Improved Contacts in Nanowire-Based Electronic Devices 有权
标题翻译：基于纳米线的电子设备中门控配置和改进接点的方法，系统和设备
公开(公告)号：US20100144103A1
公开(公告)日：2010-06-10
申请号：US12703043
申请日：2010-02-09
申请人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
发明人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
IPC分类号： H01L21/8232 , H01L21/302
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L29/785 , H01L29/78645 , H01L29/78681 , H01L29/7869 , Y10S977/762 , Y10S977/932 , Y10S977/938
摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
摘要翻译：描述了具有改进的门结构的电子设备的方法，系统和装置。电子装置包括至少一个纳米线。栅极接触沿至少一个纳米线的长度的至少一部分定位。介电材料层在栅极接触和至少一个纳米线之间。源极触点和漏极触点与至少一个纳米线接触。源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。环形第一栅极区域沿着纳米线长度的一部分包围纳米线。第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

5. 发明授权

US07473943B2 Gate configuration for nanowire electronic devices 失效
标题翻译：纳米线电子器件的栅极配置
公开(公告)号：US07473943B2
公开(公告)日：2009-01-06
申请号：US11233398
申请日：2005-09-22
申请人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
发明人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
IPC分类号： H01L29/80
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L29/785 , H01L29/78645 , H01L29/78681 , H01L29/7869 , Y10S977/762 , Y10S977/932 , Y10S977/938
摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
摘要翻译：描述了具有改进的门结构的电子设备的方法，系统和装置。电子装置包括至少一个纳米线。栅极接触沿至少一个纳米线的长度的至少一部分定位。介电材料层在栅极接触和至少一个纳米线之间。源极触点和漏极触点与至少一个纳米线接触。源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。环形第一栅极区域沿着纳米线长度的一部分包围纳米线。第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

6. 发明授权

US07701014B2 Gating configurations and improved contacts in nanowire-based electronic devices 失效
标题翻译：基于纳米线的电子设备的选通配置和改进的接触
公开(公告)号：US07701014B2
公开(公告)日：2010-04-20
申请号：US12244573
申请日：2008-10-02
申请人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
发明人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
IPC分类号： H01L27/088
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L29/785 , H01L29/78645 , H01L29/78681 , H01L29/7869 , Y10S977/762 , Y10S977/932 , Y10S977/938
摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
摘要翻译：描述了具有改进的门结构的电子设备的方法，系统和装置。电子装置包括至少一个纳米线。栅极接触沿至少一个纳米线的长度的至少一部分定位。介电材料层在栅极接触和至少一个纳米线之间。源极触点和漏极触点与至少一个纳米线接触。源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。环形第一栅极区域沿着纳米线长度的一部分包围纳米线。第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

7. 发明授权

US07871870B2 Method of fabricating gate configurations for an improved contacts in nanowire based electronic devices 有权
标题翻译：制造基于纳米线的电子器件中改进接触的栅极配置的方法
公开(公告)号：US07871870B2
公开(公告)日：2011-01-18
申请号：US12703043
申请日：2010-02-09
申请人： Shahriar Mostarshed , Jian Chen , Francisco A. Leon , Yaoling Pan , Linda T. Romano
发明人： Shahriar Mostarshed , Jian Chen , Francisco A. Leon , Yaoling Pan , Linda T. Romano
IPC分类号： H01L21/00 , H01L27/108
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L29/785 , H01L29/78645 , H01L29/78681 , H01L29/7869 , Y10S977/762 , Y10S977/932 , Y10S977/938
摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
摘要翻译：描述了具有改进的门结构的电子设备的方法，系统和装置。电子装置包括至少一个纳米线。栅极接触沿至少一个纳米线的长度的至少一部分定位。介电材料层在栅极接触和至少一个纳米线之间。源极触点和漏极触点与至少一个纳米线接触。源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。环形第一栅极区域沿着纳米线长度的一部分包围纳米线。第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

8. 发明申请

US20060081886A1 Method, system and apparatus for gating configurations and improved contacts in nanowire-based electronic devices 失效
标题翻译：用于选通配置和改进基于纳米线的电子设备中的接触的方法，系统和设备
公开(公告)号：US20060081886A1
公开(公告)日：2006-04-20
申请号：US11233398
申请日：2005-09-22
申请人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda Romano
发明人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda Romano
IPC分类号： H01L29/76
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L29/785 , H01L29/78645 , H01L29/78681 , H01L29/7869 , Y10S977/762 , Y10S977/932 , Y10S977/938
摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
摘要翻译：描述了具有改进的门结构的电子设备的方法，系统和装置。电子装置包括至少一个纳米线。栅极接触沿至少一个纳米线的长度的至少一部分定位。介电材料层在栅极接触和至少一个纳米线之间。源极触点和漏极触点与至少一个纳米线接触。源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。环形第一栅极区域沿着纳米线长度的一部分包围纳米线。第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

9. 发明申请

US20080038520A1 Methods for oriented growth of nanowires on patterned substrates 有权
公开(公告)号：US20080038520A1
公开(公告)日：2008-02-14
申请号：US11641939
申请日：2006-12-20
申请人： Yaoling Pan , Xiangfeng Duan , Robert Dubrow , Jay Goldman , Shahriar Mostarshed , Chunming Niu , Linda Romano , David Stumbo , Alice Fischer-Colbrie , Vijendra Sahi , Virginia Robbins
发明人： Yaoling Pan , Xiangfeng Duan , Robert Dubrow , Jay Goldman , Shahriar Mostarshed , Chunming Niu , Linda Romano , David Stumbo , Alice Fischer-Colbrie , Vijendra Sahi , Virginia Robbins
IPC分类号： B32B15/02 , B05D5/12
CPC分类号： C30B29/605 , B82Y30/00 , C30B11/12 , C30B29/06 , Y10T428/24917
摘要： The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors, as well as us of patterned substrates to grow oriented nanowires. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

10. 发明授权

US07105428B2 Systems and methods for nanowire growth and harvesting 有权
公开(公告)号：US07105428B2
公开(公告)日：2006-09-12
申请号：US11117703
申请日：2005-04-29
申请人： Yaoling Pan , Xiangfeng Duan , Robert S. Dubrow , Jay L. Goldman , Shahriar Mostarshed , Chunming Niu , Linda T. Romano , Dave Stumbo
发明人： Yaoling Pan , Xiangfeng Duan , Robert S. Dubrow , Jay L. Goldman , Shahriar Mostarshed , Chunming Niu , Linda T. Romano , Dave Stumbo
IPC分类号： H01L21/20 , H01L21/477 , H01L21/31 , H01L23/48 , H01L29/40 , B01J27/22 , H01L21/44
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B32/18 , C30B11/12 , C30B25/00 , C30B29/06 , C30B29/60 , C30B29/605 , H01L21/0237 , H01L21/02381 , H01L21/02422 , H01L21/02521 , H01L21/02573 , H01L21/02603 , H01L21/0262 , H01L21/02645 , H01L21/02653 , H01L29/0665 , H01L29/66477 , H01L29/78 , H01L29/7854 , H01L2924/0002 , Y10S438/962 , Y10S977/742 , Y10S977/743 , Y10S977/843 , Y10S977/891 , H01L2924/00
摘要： The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

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