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1. 发明授权

US07092038B2 Adaptive Y/C separation circuit 有权
标题翻译：自适应Y / C分离电路
公开(公告)号：US07092038B2
公开(公告)日：2006-08-15
申请号：US10370450
申请日：2003-02-24
申请人： Yang-Hong Shih , Ming-Hsiu Lee
发明人： Yang-Hong Shih , Ming-Hsiu Lee
IPC分类号： H04N9/78
CPC分类号： H04N9/78
摘要： The present invention provides an adaptive Y/C separation circuit for video signal processing that is capable of correcting previous color discrepancy in separating the luminance (Y) and chrominance (C) signals from the color video signals. In the process, the correlation of video signals on referencing scanning lines is analyzed by transposing the chrominance signals onto a two-dimensional UV plane. A correlation coefficient is obtained through the analysis for adjusting the video signals in the direction of the actual chrominance level, thus separating the luminance and chrominance signals with relatively low cost circuit implementation.
摘要翻译：本发明提供了一种用于视频信号处理的自适应Y / C分离电路，其能够校正从彩色视频信号中分离亮度（Y）和色度（C）信号的先前颜色差异。在该过程中，通过将色度信号转换到二维UV平面来分析参考扫描线上的视频信号的相关性。通过用于在实际色度电平方向上调整视频信号的分析获得相关系数，从而以相对低成本的电路实现分离亮度和色度信号。

2. 发明授权

US09070860B2 Resistance memory cell and operation method thereof 有权
标题翻译：电阻记忆单元及其操作方法
公开(公告)号：US09070860B2
公开(公告)日：2015-06-30
申请号：US13601209
申请日：2012-08-31
申请人： Wei-Chih Chien , Ming-Hsiu Lee
发明人： Wei-Chih Chien , Ming-Hsiu Lee
IPC分类号： H01L45/00 , G11C13/00 , G11C29/50
CPC分类号： H01L45/08 , G11C13/0007 , G11C13/0069 , G11C13/0097 , G11C29/50008 , G11C2029/5002 , G11C2213/72 , H01L45/1206 , H01L45/1233 , H01L45/1286 , H01L45/146
摘要： A resistance memory cell is provided and includes a first electrode, a tungsten metal layer, a metal oxide layer, and a second electrode. The tungsten metal layer is disposed on the first electrode. The metal oxide layer is disposed on the tungsten metal layer. The second electrode includes a first connection pad, a second connection pad, and a bridge portion electrically connected between the first connection pad and the second connection pad. The bridge portion is disposed on the metal oxide layer or surrounds the metal oxide layer. The resistance memory cell adjusts a resistivity of the metal oxide layer through a first current path, passing through the metal oxide layer and the tungsten metal layer, or a second current path extending from the first connection pad to the second connection pad.
摘要翻译：提供了一种电阻记忆单元，包括第一电极，钨金属层，金属氧化物层和第二电极。钨金属层设置在第一电极上。金属氧化物层设置在钨金属层上。第二电极包括第一连接焊盘，第二连接焊盘和电连接在第一连接焊盘和第二连接焊盘之间的桥接部分。桥接部分设置在金属氧化物层上或围绕金属氧化物层。电阻存储单元通过穿过金属氧化物层和钨金属层的第一电流路径或从第一连接焊盘延伸到第二连接焊盘的第二电流路径来调节金属氧化物层的电阻率。

3. 发明授权

US08699258B2 Verification algorithm for metal-oxide resistive memory 有权
标题翻译：金属氧化物电阻记忆体验证算法
公开(公告)号：US08699258B2
公开(公告)日：2014-04-15
申请号：US13212493
申请日：2011-08-18
申请人： Wei-Chih Chien , Ming-Hsiu Lee , Yan-Ru Chen
发明人： Wei-Chih Chien , Ming-Hsiu Lee , Yan-Ru Chen
IPC分类号： G11C11/00
CPC分类号： G11C7/1045 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0092 , G11C2213/79
摘要： Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.
摘要翻译：描述了用于操作这种装置的存储器件和方法，其可以有效地将阵列中的金属氧化物存储元件编程，同时还避免施加不必要的高电压脉冲。本文描述的编程操作包括在金属氧化物存储元件上施加较低电压脉冲以建立期望的电阻状态，并且仅当较低电压脉冲不足以对存储元件进行编程时才施加较高电压脉冲。在这样做时，可以避免与在存储元件上施加不必要的高电压有关的问题。

4. 发明申请

US20120188813A1 VERIFICATION ALGORITHM FOR METAL-OXIDE RESISTIVE MEMORY 有权
标题翻译：用于金属氧化物电阻记忆的验证算法
公开(公告)号：US20120188813A1
公开(公告)日：2012-07-26
申请号：US13212493
申请日：2011-08-18
申请人： Wei-Chih Chien , Ming-Hsiu Lee , Yan-Ru Chen
发明人： Wei-Chih Chien , Ming-Hsiu Lee , Yan-Ru Chen
IPC分类号： G11C11/21
CPC分类号： G11C7/1045 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0092 , G11C2213/79
摘要： Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.
摘要翻译：描述了用于操作这种装置的存储器件和方法，其可以有效地将阵列中的金属氧化物存储元件编程，同时还避免施加不必要的高电压脉冲。本文描述的编程操作包括在金属氧化物存储元件上施加较低电压脉冲以建立期望的电阻状态，并且仅当较低电压脉冲不足以对存储元件进行编程时才施加较高电压脉冲。在这样做时，可以避免与在存储元件上施加不必要的高电压有关的问题。

5. 发明授权

US08178407B2 Systems and methods for a high density, compact memory array 有权
标题翻译：用于高密度，紧凑型存储器阵列的系统和方法
公开(公告)号：US08178407B2
公开(公告)日：2012-05-15
申请号：US12561395
申请日：2009-09-17
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

6. 发明申请

US20100295009A1 Phase Change Memory Cells Having Vertical Channel Access Transistor and Memory Plane 有权
标题翻译：具有垂直通道访问晶体管和存储器平面的相变存储单元
公开(公告)号：US20100295009A1
公开(公告)日：2010-11-25
申请号：US12471287
申请日：2009-05-22
申请人： Hsiang-Lan Lung , Chung H. Lam , Ming-Hsiu Lee , Bipin Rajendran
发明人： Hsiang-Lan Lung , Chung H. Lam , Ming-Hsiu Lee , Bipin Rajendran
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L27/101 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的对应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻多行字线中的字线。相应的字线用作场效应晶体管的栅极。电介质将对应的字线与沟道区分开。存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

7. 发明授权

US07817472B2 Operating method of memory device 有权
标题翻译：存储器件的操作方法
公开(公告)号：US07817472B2
公开(公告)日：2010-10-19
申请号：US12169155
申请日：2008-07-08
申请人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
发明人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/14
摘要： An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array.
摘要翻译：提供了一种存储器阵列的操作方法。操作方法包括执行编程操作。通过将第一电压施加到存储器阵列的位线并将第二电压施加到存储器阵列的多个字线来执行编程操作，以同时对存储器阵列中的多个选择的存储器单元进行编程。

8. 发明授权

US07787294B2 Operating method of memory 有权
标题翻译：记忆的操作方法
公开(公告)号：US07787294B2
公开(公告)日：2010-08-31
申请号：US12031189
申请日：2008-02-14
申请人： Ming-Chang Kuo , Ming-Hsiu Lee
发明人： Ming-Chang Kuo , Ming-Hsiu Lee
IPC分类号： G11C16/04
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0491
摘要： An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state.
摘要翻译：提供了一种存储器的操作方法。存储器包括由多个存储单元，多个位线和多个字线组成的存储单元阵列。在编程存储器期间，选择一列存储单元。在对应于所选列的存储单元的第一源极/漏极区域和相邻的两个位线的位线之间分别产生电压差，偏置分别施加到与每个存储单元的控制栅极相对应的字线在所选择的列中，以允许存储器单元的数据位处于多个预定编程状态，并且在相邻列中的每个存储器单元的不可用位与所选择的列共享与不可用状态相同的位线。

9. 发明申请

US20100091558A1 Dielectric-Sandwiched Pillar Memory Device 有权
标题翻译：介质三通支柱存储器件
公开(公告)号：US20100091558A1
公开(公告)日：2010-04-15
申请号：US12249178
申请日：2008-10-10
申请人： Ming-Hsiu Lee , Chieh-Fang Chen
发明人： Ming-Hsiu Lee , Chieh-Fang Chen
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C5/063 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C2213/34 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A memory device includes bottom and top electrode structures and a memory cell therebetween. The memory cell comprises bottom and top memory elements and a dielectric element therebetween. A lower resistance conduction path is formed through the dielectric element. The dielectric element may have an outer edge and a central portion, the outer edge being thicker than the central portion. To make a memory device, an electrical pulse is applied through the memory cell to form a conduction path through the dielectric element. A passivation element may be formed by oxidizing the outer surface of the memory cell which may also enlarge the outer edge of the dielectric element.
摘要翻译：存储器件包括底部和顶部电极结构以及它们之间的存储单元。存储单元包括底部和顶部存储器元件以及它们之间的介电元件。通过介电元件形成较低的电阻传导路径。电介质元件可以具有外边缘和中心部分，外边缘比中心部分厚。为了制造存储器件，通过存储器单元施加电脉冲以形成穿过介质元件的传导路径。可以通过氧化存储单元的外表面来形成钝化元件，该外表面也可以增大电介质元件的外边缘。

10. 发明申请

US20090207658A1 OPERATING METHOD OF MEMORY DEVICE 有权
标题翻译：存储器件的操作方法
公开(公告)号：US20090207658A1
公开(公告)日：2009-08-20
申请号：US12169155
申请日：2008-07-08
申请人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
发明人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/14
摘要： An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array
摘要翻译：提供了一种存储器阵列的操作方法。操作方法包括执行编程操作。通过将第一电压施加到存储器阵列的位线并将第二电压施加到存储器阵列的多个字线来执行编程操作，以同时编程存储器阵列中的多个选择的存储器单元

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