专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080084752A1 SYSTEMS UTILIZING VARIABLE PROGRAM VOLTAGE INCREMENT VALUES IN NON-VOLATILE MEMORY PROGRAM OPERATIONS 有权
标题翻译：在非易失性存储器程序运行中利用可变程序电压增量值的系统
公开(公告)号：US20080084752A1
公开(公告)日：2008-04-10
申请号：US11548267
申请日：2006-10-10
申请人： Yan Li , Fanglin Zhang , Toru Miwa , Farookh Moogat
发明人： Yan Li , Fanglin Zhang , Toru Miwa , Farookh Moogat
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/3481
摘要： The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.
摘要翻译：与其他状态相比，多状态非易失性闪存器件中的最低编程状态可能会受到位线到位线电容电荷耦合的增加的影响。当将存储器单元编程到最低可编程状态时，可以使用较小的值将增加的电压脉冲施加到存储单元的编程电压递增。施加电压的较小增量允许更高的精度和更窄的阈值电压分布，以补偿编程到该状态的单元所经历的不成比例的电荷耦合。在一些实现中从较低页切换到上页编程时，可以使用较小的增量值。在流水线编程架构中，形成物理页面的单元存储两个逻辑页面的数据和一个逻辑页面的编程，在接收另一个逻辑页面的数据之前开始，当从第一个逻辑页面的编程切换到编程时，增量值可以增加同时页面。

2. 发明授权

US07450426B2 Systems utilizing variable program voltage increment values in non-volatile memory program operations 有权
标题翻译：在非易失性存储器程序操作中利用可变程序电压增量值的系统
公开(公告)号：US07450426B2
公开(公告)日：2008-11-11
申请号：US11548267
申请日：2006-10-10
申请人： Yan Li , Fanglin Zhang , Toru Miwa , Farookh Moogat
发明人： Yan Li , Fanglin Zhang , Toru Miwa , Farookh Moogat
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/3481
摘要： The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.
摘要翻译：与其他状态相比，多状态非易失性闪存器件中的最低编程状态可能会受到位线到位线电容电荷耦合的增加的影响。当将存储器单元编程到最低可编程状态时，可以使用较小的值将增加的电压脉冲施加到存储单元的编程电压递增。施加电压的较小增量允许更高的精度和更窄的阈值电压分布，以补偿编程到该状态的单元所经历的不成比例的电荷耦合。在一些实现中从较低页切换到上页编程时，可以使用较小的增量值。在流水线编程架构中，形成物理页面的单元存储两个逻辑页面的数据和一个逻辑页面的编程，在接收另一个逻辑页面的数据之前开始，当从第一个逻辑页面的编程切换到编程时，增量值可以增加同时页面。

3. 发明申请

US20080084751A1 VARIABLE PROGRAM VOLTAGE INCREMENT VALUES IN NON-VOLATILE MEMORY PROGRAM OPERATIONS 有权
标题翻译：非易失性存储器程序运行中可变程序电压增量值
公开(公告)号：US20080084751A1
公开(公告)日：2008-04-10
申请号：US11548264
申请日：2006-10-10
申请人： Yan Li , Fanglin Zhang , Toru Miwa , Farookh Moogat
发明人： Yan Li , Fanglin Zhang , Toru Miwa , Farookh Moogat
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/3481
摘要： The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.
摘要翻译：与其他状态相比，多状态非易失性闪存器件中的最低编程状态可能会受到位线到位线电容电荷耦合的增加的影响。当将存储器单元编程到最低可编程状态时，可以使用较小的值将增加的电压脉冲施加到存储单元的编程电压递增。施加电压的较小增量允许更高的精度和更窄的阈值电压分布，以补偿编程到该状态的单元所经历的不成比例的电荷耦合。在一些实现中从较低页切换到上页编程时，可以使用较小的增量值。在流水线编程架构中，形成物理页面的单元存储两个逻辑页面的数据和一个逻辑页面的编程在接收另一个逻辑页面的数据之前开始，当从第一个逻辑页面的编程切换到编程时，可以增加增量值同时页面。

4. 发明授权

US07474561B2 Variable program voltage increment values in non-volatile memory program operations 有权
标题翻译：非易失性存储器程序操作中的可编程电压增量值
公开(公告)号：US07474561B2
公开(公告)日：2009-01-06
申请号：US11548264
申请日：2006-10-10
申请人： Yan Li , Fanglin Zhang , Toru Miwa , Farookh Moogat
发明人： Yan Li , Fanglin Zhang , Toru Miwa , Farookh Moogat
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/3481
摘要： The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.
摘要翻译：与其他状态相比，多状态非易失性闪存器件中的最低编程状态可能会受到位线到位线电容电荷耦合的增加的影响。当将存储器单元编程到最低可编程状态时，可以使用较小的值将增加的电压脉冲施加到存储单元的编程电压递增。施加电压的较小增量允许更高的精度和更窄的阈值电压分布，以补偿编程到该状态的单元所经历的不成比例的电荷耦合。在一些实现中从较低页切换到上页编程时，可以使用较小的增量值。在流水线编程架构中，形成物理页面的单元存储两个逻辑页面的数据和一个逻辑页面的编程，在接收另一个逻辑页面的数据之前开始，当从第一个逻辑页面的编程切换到编程时，增量值可以增加同时页面。

5. 发明授权

US07974134B2 Voltage generator to compensate sense amplifier trip point over temperature in non-volatile memory 有权
标题翻译：电压发生器补偿非易失性存储器中读出放大器跳变点温度过高
公开(公告)号：US07974134B2
公开(公告)日：2011-07-05
申请号：US12617860
申请日：2009-11-13
申请人： Fanglin Zhang , Jong Park , Man Mui , Alexander Chu , Seungpil Lee
发明人： Fanglin Zhang , Jong Park , Man Mui , Alexander Chu , Seungpil Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C11/5642
摘要： In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared to a trip point, which is the threshold voltage of a voltage-sensing transistor. To account for temperature variations and manufacturing process variations, the voltage generator includes a transistor which is matched to the voltage-setting transistor, and a transistor which is matched to the voltage-sensing transistor. As a result, a voltage swing between the initial voltage and the trip point is constant, even as the initial voltage and trip point vary. In a particular implementation, the voltage generator uses a cascode current mirror circuit, and receives a reference current from a band gap voltage circuit.
摘要翻译：在非易失性存储器系统中，电压发生器向用于感测电路的电压设置晶体管的栅极提供电压，以在感测节点处设置初始电压。在感测周期结束时，将感测节点的最终电压与作为电压感测晶体管的阈值电压的跳变点进行比较。为了解决温度变化和制造工艺变化，电压发生器包括与电压设定晶体管相匹配的晶体管和与电压感测晶体管匹配的晶体管。结果，即使初始电压和跳变点变化，初始电压和跳闸点之间的电压摆动也是恒定的。在特定实施方案中，电压发生器使用共源共栅电流镜电路，并从带隙电压电路接收参考电流。

6. 发明申请

US20090296488A1 High Speed Sense Amplifier Array and Method for Nonvolatile Memory 有权
标题翻译：高速感应放大器阵列和非易失性存储器的方法
公开(公告)号：US20090296488A1
公开(公告)日：2009-12-03
申请号：US12128535
申请日：2008-05-28
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
IPC分类号： G11C16/26 , G11C7/00
CPC分类号： G11C16/26 , G11C7/02 , G11C7/06 , G11C11/5642 , G11C16/0483 , G11C2211/5634
摘要： Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
摘要翻译：提供了用于感测并联感测的一组非易失性存储单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。预充电电路耦合到用于将节点充电到初始电压的节点。中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

7. 发明申请

US20110116320A1 VOLTAGE GENERATOR TO COMPENSATE SENSE AMPLIFIER TRIP POINT OVER TEMPERATURE IN NON-VOLATILE MEMORY 有权
标题翻译：电压发生器在非易失性存储器中补偿感测放大器触发点温度
公开(公告)号：US20110116320A1
公开(公告)日：2011-05-19
申请号：US12617860
申请日：2009-11-13
申请人： Fanglin Zhang , Jong Park , Man Mui , Alexander Chu , Seungpil Lee
发明人： Fanglin Zhang , Jong Park , Man Mui , Alexander Chu , Seungpil Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C11/5642
摘要： In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared to a trip point, which is the threshold voltage of a voltage-sensing transistor. To account for temperature variations and manufacturing process variations, the voltage generator includes a transistor which is matched to the voltage-setting transistor, and a transistor which is matched to the voltage-sensing transistor. As a result, a voltage swing between the initial voltage and the trip point is constant, even as the initial voltage and trip point vary. In a particular implementation, the voltage generator uses a cascode current mirror circuit, and receives a reference current from a band gap voltage circuit.
摘要翻译：在非易失性存储器系统中，电压发生器向用于感测电路的电压设置晶体管的栅极提供电压，以在感测节点处设置初始电压。在感测周期结束时，将感测节点的最终电压与作为电压感测晶体管的阈值电压的跳变点进行比较。为了解决温度变化和制造工艺变化，电压发生器包括与电压设定晶体管相匹配的晶体管和与电压感测晶体管匹配的晶体管。结果，即使初始电压和跳变点变化，初始电压和跳闸点之间的电压摆动也是恒定的。在特定实施方案中，电压发生器使用共源共栅电流镜电路，并从带隙电压电路接收参考电流。

8. 发明授权

US08169831B2 High speed sense amplifier array and method for non-volatile memory 有权
标题翻译：高速读出放大器阵列和非易失性存储器的方法
公开(公告)号：US08169831B2
公开(公告)日：2012-05-01
申请号：US13100164
申请日：2011-05-03
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C7/02 , G11C7/06 , G11C11/5642 , G11C16/0483 , G11C2211/5634
摘要： Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
摘要翻译：提供用于感测并联感测的一组非易失性存储器单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。预充电电路耦合到用于将节点充电到初始电压的节点。中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

9. 发明申请

US20110205804A1 High Speed Sense Amplifier Array and Method for Non-Volatile Memory 有权
标题翻译：高速感应放大器阵列和非易失性存储器的方法
公开(公告)号：US20110205804A1
公开(公告)日：2011-08-25
申请号：US13100164
申请日：2011-05-03
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
IPC分类号： G11C16/28
CPC分类号： G11C16/26 , G11C7/02 , G11C7/06 , G11C11/5642 , G11C16/0483 , G11C2211/5634
摘要： Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
摘要翻译：提供用于感测并联感测的一组非易失性存储器单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。预充电电路耦合到用于将节点充电到初始电压的节点。中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

10. 发明授权

US08582381B2 Temperature based compensation during verify operations for non-volatile storage 有权
标题翻译：用于非易失性存储的验证操作期间的温度补偿
公开(公告)号：US08582381B2
公开(公告)日：2013-11-12
申请号：US13403934
申请日：2012-02-23
申请人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
发明人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
IPC分类号： G11C7/04 , G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式