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1. 发明授权

US08169831B2 High speed sense amplifier array and method for non-volatile memory 有权
标题翻译：高速读出放大器阵列和非易失性存储器的方法
公开(公告)号：US08169831B2
公开(公告)日：2012-05-01
申请号：US13100164
申请日：2011-05-03
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C7/02 , G11C7/06 , G11C11/5642 , G11C16/0483 , G11C2211/5634
摘要： Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
摘要翻译：提供用于感测并联感测的一组非易失性存储器单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。预充电电路耦合到用于将节点充电到初始电压的节点。中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

2. 发明申请

US20110205804A1 High Speed Sense Amplifier Array and Method for Non-Volatile Memory 有权
标题翻译：高速感应放大器阵列和非易失性存储器的方法
公开(公告)号：US20110205804A1
公开(公告)日：2011-08-25
申请号：US13100164
申请日：2011-05-03
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
IPC分类号： G11C16/28
CPC分类号： G11C16/26 , G11C7/02 , G11C7/06 , G11C11/5642 , G11C16/0483 , G11C2211/5634
摘要： Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
摘要翻译：提供用于感测并联感测的一组非易失性存储器单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。预充电电路耦合到用于将节点充电到初始电压的节点。中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

3. 发明申请

US20090296488A1 High Speed Sense Amplifier Array and Method for Nonvolatile Memory 有权
标题翻译：高速感应放大器阵列和非易失性存储器的方法
公开(公告)号：US20090296488A1
公开(公告)日：2009-12-03
申请号：US12128535
申请日：2008-05-28
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
IPC分类号： G11C16/26 , G11C7/00
CPC分类号： G11C16/26 , G11C7/02 , G11C7/06 , G11C11/5642 , G11C16/0483 , G11C2211/5634
摘要： Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
摘要翻译：提供了用于感测并联感测的一组非易失性存储单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。预充电电路耦合到用于将节点充电到初始电压的节点。中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

4. 发明授权

US07957197B2 Nonvolatile memory with a current sense amplifier having a precharge circuit and a transfer gate coupled to a sense node 有权
标题翻译：具有电流检测放大器的非易失性存储器具有预充电电路和耦合到感测节点的传输栅极
公开(公告)号：US07957197B2
公开(公告)日：2011-06-07
申请号：US12128535
申请日：2008-05-28
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C7/02 , G11C7/06 , G11C11/5642 , G11C16/0483 , G11C2211/5634
摘要： Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result of the sensing to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, by which current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination of the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of this determination; and a transfer gate coupled to the data latch to supply a latched result to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
摘要翻译：提供了用于感测并联感测的一组非易失性存储器单元中的存储单元的传导电流的感测电路，并将该感测的结果提供给数据总线。预充电电路耦合到用于将节点充电到初始电压的节点。中间电路也耦合到节点并且可连接到存储器单元，来自预充电电路的电流可以被提供给存储单元。该电路还包括比较器电路，用于通过节点处的放电速率来执行导通电流的确定; 耦合到所述比较器电路以保持所述确定结果的数据锁存器; 以及传输门，耦合到数据锁存器，以将锁存的结果提供给独立于该节点的数据总线。这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

5. 发明授权

US07606076B2 Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise 有权
标题翻译：在非易失性存储器中使用下拉调节源电压来消除系统噪声
公开(公告)号：US07606076B2
公开(公告)日：2009-10-20
申请号：US12099439
申请日：2008-04-08
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Chi-Ming Wang
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Chi-Ming Wang
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/24 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3427 , G11C16/3454
摘要： A pull down circuit pulls a bit line voltage to a regulated source voltage in a non-volatile storage device during a sense operation such as a verify operation which occurs during programming. The storage device may include NAND strings which have associated bit lines and sense components, and a common source line. When a selected storage element of a NAND string has been programmed to its intended state, the bit line is locked out during subsequent verify operations which occur for other NAND strings which are not yet locked out. The pull down device is coupled to each bit line and to the common source line, whose voltage is regulated at a positive DC level, to prevent coupling of system power bus (VSS) noise from the locked out bit lines to the not yet locked out bit lines.
摘要翻译：下拉电路在诸如在编程期间发生的验证操作的感测操作期间将位线电压拉到非易失性存储设备中的稳压源电压。存储设备可以包括具有相关联的位线和感测组件的NAND串，以及公共源线。当NAND串的所选择的存储元件已被编程到其预期状态时，在对尚未被锁定的其它NAND串发生的后续验证操作期间，位线被锁定。下拉装置耦合到每个位线和公共源极线，其电压被调节在正的直流电平，以防止将系统电源总线（VSS）噪声从锁定的位线耦合到尚未锁定位线。

6. 发明申请

US20080247241A1 SENSING IN NON-VOLATILE STORAGE USING PULLDOWN TO REGULATED SOURCE VOLTAGE TO REMOVE SYSTEM NOISE 有权
标题翻译：使用推挽方式将非挥发性储存感知到调节源电压以移除系统噪声
公开(公告)号：US20080247241A1
公开(公告)日：2008-10-09
申请号：US12099439
申请日：2008-04-08
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Chi-Ming Wang
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Chi-Ming Wang
IPC分类号： G11C16/06
CPC分类号： G11C16/24 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3427 , G11C16/3454
摘要： A pull down circuit pulls a bit line voltage to a regulated source voltage in a non-volatile storage device during a sense operation such as a verify operation which occurs during programming. The storage device may include NAND strings which have associated bit lines and sense components, and a common source line. When a selected storage element of a NAND string has been programmed to its intended state, the bit line is locked out during subsequent verify operations which occur for other NAND strings which are not yet locked out. The pull down device is coupled to each bit line and to the common source line, whose voltage is regulated at a positive DC level, to prevent coupling of system power bus (VSS) noise from the locked out bit lines to the not yet locked out bit lines.
摘要翻译：下拉电路在诸如在编程期间发生的验证操作的感测操作期间将位线电压拉到非易失性存储设备中的稳压源电压。存储设备可以包括具有相关联的位线和感测组件的NAND串，以及公共源线。当NAND串的所选择的存储元件已被编程到其预期状态时，在对尚未被锁定的其它NAND串发生的后续验证操作期间，位线被锁定。下拉装置耦合到每个位线和公共源极线，其电压被调节为正的直流电平，以防止系统电源总线（V SS SS）噪声与被锁定的位线到尚未锁定的位线。

7. 发明申请

US20100309720A1 Structure and Method for Shuffling Data Within Non-Volatile Memory Devices 有权
标题翻译：在非易失性存储器件中进行数据混合的结构和方法
公开(公告)号：US20100309720A1
公开(公告)日：2010-12-09
申请号：US12635449
申请日：2009-12-10
申请人： Bo Liu , Yan Li , Alexander Kwok-Tung Mak , Chi-Ming Wang , Eugene Jinglun Tam , Kwang-ho Kim
发明人： Bo Liu , Yan Li , Alexander Kwok-Tung Mak , Chi-Ming Wang , Eugene Jinglun Tam , Kwang-ho Kim
IPC分类号： G11C16/04 , G11C7/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/34 , G11C2211/5641 , G11C2211/5642
摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.
摘要翻译：描述用于在多状态非易失性存储器中读取和写入数据的技术。数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。还描述了数据“展开”的相应的读取技术。这些技术进一步允许在控制器上用纠错码（ECC）编码数据，该数据在将数据传送到存储器以二进制形式写入之前考虑到其最终的多状态存储。还提出了允许这种“折叠”操作的寄存器结构。一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

8. 发明授权

US07339822B2 Current-limited latch 有权
公开(公告)号：US07339822B2
公开(公告)日：2008-03-04
申请号：US10313738
申请日：2002-12-06
申请人： Chi-Ming Wang , Kuo-Lung Chen , Shouchang Tsao
发明人： Chi-Ming Wang , Kuo-Lung Chen , Shouchang Tsao
IPC分类号： G11C16/04
CPC分类号： G11C16/12
摘要： A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A current mirroring scheme limits current supplied to the latch. This reduces a difference of the two supplies, positive voltage, ground, or negative voltages, during data changes. The circuit provides smaller device sizes and fast speeds when data changes in the latch, while also providing lower power consumption. The technique provides greater benefits as the voltage difference between the two power supplies is greater.

9. 发明授权

US06977844B2 Method of reducing disturbs in non-volatile memory 失效
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06977844B2
公开(公告)日：2005-12-20
申请号：US11054084
申请日：2005-02-08
申请人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

10. 发明授权

US06888752B2 Method of reducing disturbs in non-volatile memory 有权
公开(公告)号：US06888752B2
公开(公告)日：2005-05-03
申请号：US10613098
申请日：2003-07-01
申请人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

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