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1. 发明授权

US07955981B2 Method of making a two-terminal non-volatile memory pillar device with rounded corner 有权
标题翻译：制造具有圆角的双端非易失性存储柱装置的方法
公开(公告)号：US07955981B2
公开(公告)日：2011-06-07
申请号：US12458091
申请日：2009-06-30
申请人： Xiying Chen , Huiwen Xu , Chuanbin Pan
发明人： Xiying Chen , Huiwen Xu , Chuanbin Pan
IPC分类号： H01L21/302
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1675
摘要： A non-volatile memory device includes a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell containing a steering element and a storage element and at least one of a top corner or a bottom corner of each of the plurality of pillars is rounded. A method of making non-volatile memory device includes forming a stack of device layers, and patterning the stack to form a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell that contains a steering element and a storage element, and where at least one of top corner or bottom corner of each of the plurality of pillars is rounded.
摘要翻译：非易失性存储器件包括多个支柱，其中多个支柱中的每个支柱包含含有转向元件和存储元件的非易失性存储单元，并且每个的顶角或底角中的至少一个多个柱子是圆形的。制造非易失性存储器件的方法包括形成器件层堆叠，以及图案化堆叠以形成多个柱，其中多个柱中的每个柱包含含有转向元件和存储器的非易失性存储单元并且其中所述多个柱中的每一个的顶角或底角中的至少一个是圆形的。

2. 发明授权

US08592793B2 Electrode diffusions in two-terminal non-volatile memory devices 有权
标题翻译：双端非易失性存储器件中的电极扩散
公开(公告)号：US08592793B2
公开(公告)日：2013-11-26
申请号：US13100657
申请日：2011-05-04
申请人： Xiying Chen , Huiwen Xu , Chuanbin Pan
发明人： Xiying Chen , Huiwen Xu , Chuanbin Pan
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1675
摘要： A non-volatile memory device includes a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell containing a steering element and a storage element and at least one of a top corner or a bottom corner of each of the plurality of pillars is rounded. A method of making non-volatile memory device includes forming a stack of device layers, and patterning the stack to form a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell that contains a steering element and a storage element, and where at least one of top corner or bottom corner of each of the plurality of pillars is rounded.
摘要翻译：非易失性存储器件包括多个支柱，其中多个支柱中的每个支柱包含含有转向元件和存储元件的非易失性存储单元，并且每个的顶角或底角中的至少一个多个柱子是圆形的。制造非易失性存储器件的方法包括形成器件层堆叠，以及图案化堆叠以形成多个柱，其中多个柱中的每个柱包含含有转向元件和存储器的非易失性存储单元并且其中所述多个柱中的每一个的顶角或底角中的至少一个是圆形的。

3. 发明申请

US20110169126A1 In-situ passivation methods to improve performance of polysilicon diode 有权
标题翻译：原位钝化方法提高多晶硅二极管的性能
公开(公告)号：US20110169126A1
公开(公告)日：2011-07-14
申请号：US12654927
申请日：2010-01-08
申请人： Xiying Chen , Kun Hou , Chuanbin Pan , Abhijit Bandyopadhyay , Yung-Tin Chen
发明人： Xiying Chen , Kun Hou , Chuanbin Pan , Abhijit Bandyopadhyay , Yung-Tin Chen
IPC分类号： H01L29/68 , H01L21/02 , H01L21/329
CPC分类号： H01L29/8615 , G11C13/003 , G11C2213/72 , H01L27/1021 , H01L27/2409 , H01L29/6609 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A nonvolatile memory cell including a storage element in series with a diode steering element. At least one interface of the diode steering element is passivated.
摘要翻译：一种非易失性存储单元，包括与二极管转向元件串联的存储元件。二极管控制元件的至少一个界面被钝化。

4. 发明授权

US07723180B2 Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same 有权
标题翻译：含有碳储存材料的多层非易失性存储器件及其制造和使用方法
公开(公告)号：US07723180B2
公开(公告)日：2010-05-25
申请号：US12153874
申请日：2008-05-27
申请人： Xiying Chen , Chuanbin Pan , Tanmay Kumar , Er-Xuan Ping
发明人： Xiying Chen , Chuanbin Pan , Tanmay Kumar , Er-Xuan Ping
IPC分类号： H01L21/8234
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/124 , H01L45/149 , H01L45/1616 , H01L45/1675
摘要： A method of making a non-volatile memory device includes forming a first electrode, forming a steering element, forming at least one feature, forming a carbon resistivity switching material on at least one sidewall of the at least one feature such that the carbon resistivity switching material electrically contacts the steering element, and forming a second electrode.
摘要翻译：制造非易失性存储器件的方法包括形成第一电极，形成转向元件，形成至少一个特征，在至少一个特征的至少一个侧壁上形成碳电阻率切换材料，使得碳电阻率切换材料电接触转向元件，并形成第二电极。

5. 发明申请

US20090258489A1 Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same 有权
标题翻译：含有碳储存材料的多层非易失性存储器件及其制造和使用方法
公开(公告)号：US20090258489A1
公开(公告)日：2009-10-15
申请号：US12153874
申请日：2008-05-27
申请人： Xiying Chen , Chuanbin Pan , Tanmay Kumar , Er-Xuan Ping
发明人： Xiying Chen , Chuanbin Pan , Tanmay Kumar , Er-Xuan Ping
IPC分类号： H01L21/44
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/124 , H01L45/149 , H01L45/1616 , H01L45/1675
摘要： A method of making a non-volatile memory device includes forming a first electrode, forming a steering element, forming at least one feature, forming a carbon resistivity switching material on at least one sidewall of the at least one feature such that the carbon resistivity switching material electrically contacts the steering element, and forming a second electrode.
摘要翻译：制造非易失性存储器件的方法包括形成第一电极，形成转向元件，形成至少一个特征，在至少一个特征的至少一个侧壁上形成碳电阻率切换材料，使得碳电阻率切换材料电接触转向元件，并形成第二电极。

6. 发明授权

US08450181B2 In-situ passivation methods to improve performance of polysilicon diode 有权
标题翻译：原位钝化方法提高多晶硅二极管的性能
公开(公告)号：US08450181B2
公开(公告)日：2013-05-28
申请号：US12654927
申请日：2010-01-08
申请人： Xiying Chen , Kun Hou , Chuanbin Pan , Abhijit Bandyopadhyay , Yung-Tin Chen
发明人： Xiying Chen , Kun Hou , Chuanbin Pan , Abhijit Bandyopadhyay , Yung-Tin Chen
IPC分类号： H01L29/68 , H01L21/02 , H01L21/329
CPC分类号： H01L29/8615 , G11C13/003 , G11C2213/72 , H01L27/1021 , H01L27/2409 , H01L29/6609 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A nonvolatile memory cell including a storage element in series with a diode steering element. At least one interface of the diode steering element is passivated.
摘要翻译：一种非易失性存储单元，包括与二极管转向元件串联的存储元件。二极管控制元件的至少一个界面被钝化。

7. 发明申请

US20120091419A1 MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME 有权
标题翻译：具有与转向元件共享材料层的存储元件的存储单元及其形成方法
公开(公告)号：US20120091419A1
公开(公告)日：2012-04-19
申请号：US12905047
申请日：2010-10-14
申请人： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxell , Kun Hou
发明人： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxell , Kun Hou
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/146 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1616 , Y10S438/957
摘要： In some embodiments, a memory cell is provided that includes a storage element formed from an MIM stack including (1) a first conductive layer; (2) an RRS layer formed above the first conductive layer; and (3) a second conductive layer formed above the RRS layer, at least one of the first and second conductive layers comprising a first semiconductor material layer. The memory cell includes a steering element coupled to the storage element, the steering element formed from the first semiconductor material layer of the MIM stack and one or more additional material layers. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储单元，其包括由MIM堆叠形成的存储元件，所述存储元件包括：（1）第一导电层; （2）形成在第一导电层上方的RRS层; 和（3）形成在RRS层之上的第二导电层，第一和第二导电层中的至少一个包括第一半导体材料层。存储单元包括耦合到存储元件的操纵元件，由MIM堆叠的第一半导体材料层形成的操纵元件和一个或多个附加材料层。提供了许多其他方面。

8. 发明申请

US20090179310A1 Pillar devices and methods of making thereof 有权
标题翻译：支柱装置及其制造方法
公开(公告)号：US20090179310A1
公开(公告)日：2009-07-16
申请号：US12007781
申请日：2008-01-15
申请人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
发明人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
IPC分类号： H01L29/868 , H01L21/20
CPC分类号： H01L27/1021 , H01L29/8613 , H01L29/8615 , H01L29/868
摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.
摘要翻译：制造半导体器件的方法包括提供包含多个开口的绝缘层，在绝缘层中的多个开口中并在绝缘层之上形成第一半导体层，以及去除第一半导体层的第一部分，第一半导体层的第一导电类型的第二部分保留在绝缘层中的多个开口的下部，并且绝缘层中的多个开口的上部保持未填充。该方法还包括在绝缘层中的多个开口的上部和绝缘层上形成第二半导体层，以及去除位于绝缘层之上的第二半导体层的第一部分。第二半导体层的第二导电类型的第二部分保留在绝缘层中的多个开口的上部，以在多个开口中形成多个柱状二极管。

9. 发明授权

US6154366A Structures and processes for fabricating moisture resistant chip-on-flex packages 有权
标题翻译：用于制造防潮芯片柔性包装的结构和工艺
公开(公告)号：US6154366A
公开(公告)日：2000-11-28
申请号：US448066
申请日：1999-11-23
申请人： Qing Ma , Chun Mu , Harry Fujimoto , John Carruthers , Jian Li , Chuanbin Pan
发明人： Qing Ma , Chun Mu , Harry Fujimoto , John Carruthers , Jian Li , Chuanbin Pan
IPC分类号： H01L21/60 , H01L23/538 , H05K7/20
CPC分类号： H01L23/5389 , H01L23/3135 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H01L2924/15311
摘要： A chip-on-flex package which includes at least one moisture barrier layer to prevent metal corrosion and delamination of flex component layers. An exemplary microelectronic package includes a microelectronic die having an active surface and at least one side, wherein the microelectronic die active surface includes at least one contact. A flex component is attached by a first surface to the microelectronic die active surface. At least one conductive trace is disposed on a second surface of the flex component and extends through the flex component to contact at least one of the contacts. An encapsulation material is adjacent the microelectronic die side and a bottom surface of the flex component. A moisture barrier is disposed on the flex component and the conductive trace(s). A second moisture barrier may be disposed on the encapsulation material. A heat dissipation device may also be incorporated into the chip-on-flex package.
摘要翻译：一种芯片上柔性包装，其包括至少一个防潮层，以防止金属腐蚀和挠曲组分层的分层。示例性微电子封装包括具有有源表面和至少一个侧面的微电子管芯，其中所述微电子管芯有源表面包括至少一个触点。柔性部件通过第一表面附接到微电子管芯有源表面。至少一个导电迹线设置在柔性部件的第二表面上并且延伸穿过柔性部件以接触至少一个触头。封装材料邻近微电子管芯侧面和柔性部件的底部表面。防潮层设置在柔性部件和导电迹线上。第二湿气屏障可以设置在包封材料上。散热装置也可以并入到芯片上的柔性封装中。

10. 发明授权

US08987119B2 Pillar devices and methods of making thereof 有权
公开(公告)号：US08987119B2
公开(公告)日：2015-03-24
申请号：US13026381
申请日：2011-02-14
申请人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
发明人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
IPC分类号： H01L21/36 , H01L27/102 , H01L29/861 , H01L29/868
CPC分类号： H01L27/1021 , H01L29/8613 , H01L29/8615 , H01L29/868
摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.

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