专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080023752A1 BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT 审中-公开
标题翻译： BORON DOPED SiGe HALO用于NFET控制短路通道效应
公开(公告)号：US20080023752A1
公开(公告)日：2008-01-31
申请号：US11460766
申请日：2006-07-28
申请人： Xiangdong Chen , Yung Fu Chong , Zhijiong Luo , Xinlin Wang , Haining S. Yang
发明人： Xiangdong Chen , Yung Fu Chong , Zhijiong Luo , Xinlin Wang , Haining S. Yang
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1045 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： An n-type field effect transistor (NFET) and methods of forming a halo for an NFET to control the short channel effect are disclosed. One method includes forming a gate over a silicon substrate; recessing the silicon adjacent to the gate; forming a halo by epitaxially growing boron in-situ doped silicon germanium (SiGe) in the recess; and epitaxially growing silicon over the silicon germanium. Alternatively, the halo can be formed by ion implanting boron into an embedded SiGe region within the silicon substrate. The resulting NFET includes a boron doped SiGe halo embedded within the silicon substrate. The embedded SiGe layer may be a relaxed layer without inserting strain in the channel. The high solid solubility of boron in SiGe and low diffusion rate allows formation of a halo that will maintain the sharp profile, which provides better control of the short channel effect and increasing control over NFET threshold voltage roll-off.
摘要翻译：公开了一种n型场效应晶体管（NFET）和用于形成用于NFET的光晕以控制短沟道效应的方法。一种方法包括在硅衬底上形成栅极; 凹陷与栅极相邻的硅; 通过在凹槽中外延生长硼原位掺杂硅锗（SiGe）来形成卤素; 并在硅锗上外延生长硅。或者，可以通过将硼离子注入到硅衬底内的嵌入的SiGe区域中来形成卤素。所得NFET包括嵌入在硅衬底内的硼掺杂SiGe光晕。嵌入的SiGe层可以是松弛层，而不会在通道中插入应变。硼在SiGe中的高固体溶解度和低扩散速率允许形成将保持尖锐轮廓的光晕，这提供了对短通道效应的更好控制并增加了对NFET阈值电压滚降的控制。

2. 发明申请

US20110175170A1 STRUCTURE AND METHOD FOR MAKING LOW LEAKAGE AND LOW MISMATCH NMOSFET 失效
标题翻译：用于制造低漏电和低失真的NMOSFET的结构和方法
公开(公告)号：US20110175170A1
公开(公告)日：2011-07-21
申请号：US12691183
申请日：2010-01-21
申请人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
发明人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
IPC分类号： H01L29/66 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823462 , H01L21/823468 , H01L21/823857 , H01L21/823864 , H01L27/11 , H01L27/1104
摘要： An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.
摘要翻译：公开了一种改进的SRAM和制造方法。该方法包括使用氮化物层来封装PFET和逻辑NFET，保护这些器件的栅极免受氧气暴露。用于SRAM单元中的NFET在退火过程中暴露于氧气，这改变了栅极金属的有效功函数，使得阈值电压增加，而不需要增加掺杂剂浓度，这可能不利地影响问题例如由于随机掺杂剂波动，GIDL和结泄漏引起的失配。

3. 发明授权

US08697521B2 Structure and method for making low leakage and low mismatch NMOSFET 失效
标题翻译：低泄漏和低失配NMOSFET的结构和方法
公开(公告)号：US08697521B2
公开(公告)日：2014-04-15
申请号：US12691183
申请日：2010-01-21
申请人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
发明人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823462 , H01L21/823468 , H01L21/823857 , H01L21/823864 , H01L27/11 , H01L27/1104
摘要： An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.
摘要翻译：公开了一种改进的SRAM和制造方法。该方法包括使用氮化物层来封装PFET和逻辑NFET，保护这些器件的栅极免受氧气暴露。用于SRAM单元中的NFET在退火过程中暴露于氧气，这改变了栅极金属的有效功函数，使得阈值电压增加，而不需要增加掺杂剂浓度，这可能不利地影响问题例如由于随机掺杂剂波动，GIDL和结泄漏引起的失配。

4. 发明授权

US08466473B2 Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs 有权
标题翻译：具有高k /金属栅极MOSFET的Vt调谐和短沟道控制的结构和方法
公开(公告)号：US08466473B2
公开(公告)日：2013-06-18
申请号：US12960589
申请日：2010-12-06
申请人： Jin Cai , Xiangdong Chen , Xinlin Wang
发明人： Jin Cai , Xiangdong Chen , Xinlin Wang
IPC分类号： H01L31/0312 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/823807 , H01L29/1041
摘要： A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer and a non-doped semiconductor-containing channel layer; the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a polysilicon layer.
摘要翻译：提供一种半导体器件，其包括具有位于其上部区域内的阱区的半导体衬底。半导体材料堆叠位于阱区上。半导体材料堆叠包括从底部到顶部的含半导体的缓冲层和非掺杂的含半导体的沟道层; 半导体材料堆叠的含半导体的缓冲层直接位于阱区的上表面。该结构还包括直接位于非掺杂半导体沟道层的上表面上的栅极材料堆叠。本公开中采用的栅极材料堆叠包括从底部到顶部的高k栅介质层，功函数金属层和多晶硅层。

5. 发明申请

US20120138953A1 STRUCTURE AND METHOD FOR Vt TUNING AND SHORT CHANNEL CONTROL WITH HIGH K/METAL GATE MOSFETs 有权
标题翻译：具有高K /金属栅极MOSFET的调谐和短路控制的结构和方法
公开(公告)号：US20120138953A1
公开(公告)日：2012-06-07
申请号：US12960589
申请日：2010-12-06
申请人： Jin Cai , Xiangdong Chen , Xinlin Wang
发明人： Jin Cai , Xiangdong Chen , Xinlin Wang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/823807 , H01L29/1041
摘要： A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer and a non-doped semiconductor-containing channel layer; the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a polysilicon layer.
摘要翻译：提供一种半导体器件，其包括具有位于其上部区域内的阱区的半导体衬底。半导体材料堆叠位于阱区上。半导体材料堆叠包括从底部到顶部的含半导体的缓冲层和非掺杂的含半导体的沟道层; 半导体材料堆叠的含半导体的缓冲层直接位于阱区的上表面。该结构还包括直接位于非掺杂半导体沟道层的上表面上的栅极材料堆叠。本公开中采用的栅极材料堆叠包括从底部到顶部的高k栅介质层，功函数金属层和多晶硅层。

6. 发明授权

US08120058B2 High-drive current MOSFET 有权
标题翻译：高驱动电流MOSFET
公开(公告)号：US08120058B2
公开(公告)日：2012-02-21
申请号：US12607116
申请日：2009-10-28
申请人： Jae-Eun Park , Xinlin Wang , Xiangdong Chen
发明人： Jae-Eun Park , Xinlin Wang , Xiangdong Chen
IPC分类号： H01L29/739
CPC分类号： H01L29/7394 , H01L29/66325
摘要： A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.
摘要翻译：一种形成具有不对称源极和漏极的半导体器件的方法。在一个实施例中，该方法包括在具有第一导电性阱的衬底的第一部分上形成栅极结构。第二导电性的第二导电性和漏极区的源极区域形成在第一导电性的阱内，在与存在栅极结构的基板的第一部分相邻的基板的一部分中。在漏极区域内形成第二导电性的掺杂区域，以在半导体器件的漏极侧提供集成的双极晶体管，其中集电极由第一导电性的阱提供，基极由漏极区域的第二导电性和发射极由存在于漏极区域中的第二导电性的掺杂区域提供。还提供了通过上述方法形成的半导体器件。

7. 发明申请

US20110095333A1 HIGH-DRIVE CURRENT MOSFET 有权
标题翻译：高驱动电流MOSFET
公开(公告)号：US20110095333A1
公开(公告)日：2011-04-28
申请号：US12607116
申请日：2009-10-28
申请人： Jae-Eun Park , Xinlin Wang , Xiangdong Chen
发明人： Jae-Eun Park , Xinlin Wang , Xiangdong Chen
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/7394 , H01L29/66325
摘要： A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.
摘要翻译：一种形成具有不对称源极和漏极的半导体器件的方法。在一个实施例中，该方法包括在具有第一导电性阱的衬底的第一部分上形成栅极结构。第二导电性的第二导电性和漏极区的源极区域形成在第一导电性的阱内，在与存在栅极结构的基板的第一部分相邻的基板的一部分中。在漏极区域内形成第二导电性的掺杂区域，以在半导体器件的漏极侧提供集成的双极晶体管，其中集电极由第一导电性的阱提供，基极由漏极区域的第二导电性和发射极由存在于漏极区域中的第二导电性的掺杂区域提供。还提供了通过上述方法形成的半导体器件。

8. 发明授权

US07692959B2 Multilayer storage class memory using externally heated phase change material 有权
标题翻译：使用外部加热相变材料的多层存储类存储器
公开(公告)号：US07692959B2
公开(公告)日：2010-04-06
申请号：US12107338
申请日：2008-04-22
申请人： Lia Krusin-Elbaum , Bruce G Elmegreen , Dennis M. Newns , Xinlin Wang
发明人： Lia Krusin-Elbaum , Bruce G Elmegreen , Dennis M. Newns , Xinlin Wang
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/008 , G11C2213/71 , G11C2213/72 , G11C2213/74 , H01L27/2409 , H01L27/2445 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A multi-layer, phase change material (PCM) memory apparatus includes a plurality of semiconductor layers sequentially formed over a base substrate, wherein each layer comprises an array of memory cells formed therein, each memory cell further including a PCM element, a first diode serving as a heater diode in thermal proximity to the PCM element and configured to program the PCM element to one of a low resistance crystalline state and a high resistance amorphous state, and a second diode serving a sense diode for a current path used in reading the state of the PCM element; the base substrate further including decoding, programming and sensing circuitry formed therein, with each of the plurality of semiconductor layers spaced by an insulating layer; and intralayer wiring for communication between the base substrate circuitry and the array of memory cells in each of the semiconductor layers.
摘要翻译：多层相变材料（PCM）存储装置包括顺序地形成在基底基板上的多个半导体层，其中每个层包括形成在其中的存储单元的阵列，每个存储单元还包括PCM元件，第一二极管用作加热二极管，其热量接近PCM元件并且被配置为将PCM元件编程为低电阻晶体状态和高电阻非晶态之一，以及用于读取电流路径中的电流路径的感测二极管的第二二极管 PCM元素的状态; 所述基底基板还包括其中形成的解码，编程和感测电路，所述多个半导体层中的每一个由绝缘层隔开; 以及用于在基底基板电路和每个半导体层中的存储器单元阵列之间进行通信的层内布线。

9. 发明授权

US07385257B2 Hybrid orientation SOI substrates, and method for forming the same 有权
标题翻译：混合取向SOI衬底及其形成方法
公开(公告)号：US07385257B2
公开(公告)日：2008-06-10
申请号：US11411280
申请日：2006-04-26
申请人： Meikei Ieong , Xinlin Wang , Min Yang
发明人： Meikei Ieong , Xinlin Wang , Min Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility.
摘要翻译：本发明涉及一种包含具有一个或多个第一器件区域的基底半导体衬底和位于基底半导体衬底之上的一个或多个第二器件区域的混合取向绝缘体上半导体（SOI）衬底结构。一个或多个第一器件区域包括具有位于顶部的第一半导体器件层的绝缘体层。一个或多个第二器件区域包括具有位于顶部的第二半导体器件层的反掺杂半导体层。第一和第二半导体器件层具有不同的晶体取向。优选地，第一（或第二）器件区域是n-FET器件区域，并且第一半导体器件层具有增强电子迁移率的晶体取向，而第二（或第一）器件区域是p-FET器件区域，并且第二半导体器件层具有增强空穴迁移率的不同的表面结晶取向。

10. 发明申请

US20080128766A1 MOSFET STRUCTURE WITH ULTRA-LOW K SPACER 审中-公开
标题翻译： MOSFET结构与超低K间隔
公开(公告)号：US20080128766A1
公开(公告)日：2008-06-05
申请号：US12030921
申请日：2008-02-14
申请人： Elbert E. Huang , Philip J. Oldiges , Ghavam G. Shahidi , Christy S. Tyberg , Xinlin Wang , Robert L. Wisnieff
发明人： Elbert E. Huang , Philip J. Oldiges , Ghavam G. Shahidi , Christy S. Tyberg , Xinlin Wang , Robert L. Wisnieff
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/4991 , H01L29/4983 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.
摘要翻译： MOSFET结构和制造该结构的方法包括多层侧壁间隔物，以抑制栅极导体和源极/漏极延伸之间的寄生重叠电容，而不降低驱动电流，从而影响整体MOSFET性能。多层侧壁间隔物形成有介电常数等于1的间隙层和可渗透的低K（例如，小于3.5）的电介质层。或者，多层侧壁间隔物形成有介电常数值小于约三的第一L形介电层和第二电介质层。多层间隔物也可以具有第三氮化物或氧化物隔离层。该第三间隔层提供增加的结构完整性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式