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1. 发明申请

US20140084975A1 VOLTAGE TRANSLATION CIRCUIT 有权
标题翻译：电压转换电路
公开(公告)号：US20140084975A1
公开(公告)日：2014-03-27
申请号：US13627327
申请日：2012-09-26
申请人： XINGHAI TANG , Gayathri A. Bhagavatheeswaran , Hector Sanchez
发明人： XINGHAI TANG , Gayathri A. Bhagavatheeswaran , Hector Sanchez
IPC分类号： G05F3/02 , H03L7/06
CPC分类号： H03L7/0995
摘要： A voltage translation circuit (116) provides an output analog voltage signal that has a translated voltage of the voltage of an input analog voltage signal over a range of values of the input analog voltage signal. The voltage translation circuit includes an input stage (202) having a circuit node and an input transistor (210) coupled between the circuit node and a power supply terminal, wherein a gate of the input transistor is coupled to receive the input analog voltage signal; a current path circuit (204) in parallel with the input transistor, wherein the current path includes a first transistor coupled between the circuit node and the power supply terminal; and a circuit coupled to provide a variable body bias voltage to a body of the first transistor.
摘要翻译：电压转换电路（116）提供输出模拟电压信号，其在输入模拟电压信号的值的范围内具有输入模拟电压信号的电压的转换电压。电压转换电路包括具有电路节点和耦合在电路节点与电源端子之间的输入晶体管（210）的输入级（202），其中输入晶体管的栅极耦合以接收输入模拟电压信号; 与所述输入晶体管并联的电流路径电路（204），其中所述电流路径包括耦合在所述电路节点和所述电源端子之间的第一晶体管; 以及耦合以向第一晶体管的主体提供可变主体偏置电压的电路。

2. 发明授权

US08018259B2 Phase-locked loop having a feedback clock detector circuit and method therefor 有权
标题翻译：锁相环具有反馈时钟检测电路及其方法
公开(公告)号：US08018259B2
公开(公告)日：2011-09-13
申请号：US12695461
申请日：2010-01-28
申请人： Hector Sanchez , Gayathri A. Bhagavatheeswaran , Xinghai Tang
发明人： Hector Sanchez , Gayathri A. Bhagavatheeswaran , Xinghai Tang
IPC分类号： H03L7/06
CPC分类号： H03L7/14
摘要： A method for a phase-locked loop (PLL) in an integrated circuit, wherein the PLL comprises a voltage-controlled oscillator (VCO). The method includes, in a training mode: (1) setting a control voltage of the VCO at a first voltage level; (2) increasing the control voltage of the VCO from the first voltage level to a second voltage level, until a loss of the feedback signal is detected; and (3) storing an indicator value corresponding to the second voltage level of the control voltage of the VCO. The method further includes, in a normal mode: (1) monitoring a voltage level of the control voltage of the VCO by generating a monitored indicator value corresponding to the voltage level of the control voltage of the VCO; and (2) asserting the loss of feedback signal based on a comparison of the monitored indicator value and the indicator value.
摘要翻译：一种用于集成电路中锁相环（PLL）的方法，其中PLL包括压控振荡器（VCO）。该方法包括：在训练模式中：（1）将VCO的控制电压设置在第一电压电平; （2）将VCO的控制电压从第一电压电平提高到第二电压电平，直到检测到反馈信号的损失; 和（3）存储对应于VCO的控制电压的第二电压电平的指标值。该方法还包括：在正常模式中：（1）通过产生对应于VCO的控制电压的电压电平的监视的指示值监视VCO的控制电压的电压电平; 和（2）基于所监视的指标值与指标值的比较来确定反馈信号的损失。

3. 发明授权

US08558591B1 Phase locked loop with power supply control 有权
标题翻译：带电源控制的锁相环
公开(公告)号：US08558591B1
公开(公告)日：2013-10-15
申请号：US13629643
申请日：2012-09-28
申请人： Hector Sanchez , Xinghai Tang , Gayathri A. Bhagavatheeswaran
发明人： Hector Sanchez , Xinghai Tang , Gayathri A. Bhagavatheeswaran
IPC分类号： H03L7/06
CPC分类号： H03L7/18
摘要： A phase locked loop (PLL) includes a phase frequency detector powered by a first analog supply voltage; a charge pump powered by a second analog supply voltage, different from the first analog supply voltage; a voltage controlled oscillator (VCO) powered by a third analog supply voltage, different from the first and second analog supply voltages, wherein a frequency of the VCO is controlled by a control voltage; and a supply voltage provider having a first circuit node coupled to a fourth analog supply voltage, a second circuit node which provides the first analog supply voltage, a third circuit node which provides the second analog supply voltage, and a fourth circuit node which provides the third analog supply voltage, and a current compensator coupled to one of the second, third, or fourth circuit nodes, wherein the current compensator provides a variable current draw based on the control voltage.
摘要翻译：锁相环（PLL）包括由第一模拟电源电压供电的相位频率检测器; 由第一模拟电源电压供电的电荷泵，与第一模拟电源电压不同; 由与第一和第二模拟电源电压不同的第三模拟电源电压供电的压控振荡器（VCO），其中VCO的频率由控制电压控制; 以及电源电压提供器，具有耦合到第四模拟电源电压的第一电路节点，提供第一模拟电源电压的第二电路节点，提供第二模拟电源电压的第三电路节点和提供第二模拟电源电压的第四电路节点，第三模拟电源电压和耦合到第二，第三或第四电路节点之一的电流补偿器，其中电流补偿器基于控制电压提供可变电流汲取。

4. 发明授权

US09209819B2 Phase locked loop with burn-in mode 有权
标题翻译：带有老化模式的锁相环
公开(公告)号：US09209819B2
公开(公告)日：2015-12-08
申请号：US13627333
申请日：2012-09-26
申请人： Xinghai Tang , Gayathri A. Bhagavatheeswaran , Hector Sanchez
发明人： Xinghai Tang , Gayathri A. Bhagavatheeswaran , Hector Sanchez
IPC分类号： H03L7/06 , H03L7/089 , H03L7/099
CPC分类号： H03L7/0891 , H03L7/0995
摘要： A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode.
摘要翻译：具有正常模式和老化模式的锁相环。逻辑部分耦合到逻辑电源端子并且包括耦合到相位频率检测器的时钟接收器。模拟部分具有耦合到相位频率检测器和模拟电源端子的电荷泵。模拟部分还具有耦合到模拟节点处的电荷泵和模拟电源端子的压控振荡器。锁相环具有在老化模式期间耦合到模拟节点的节点控制电路，其控制在模拟节点处的电压足够低于模拟电源端子处的电压，以避免电荷泵的过度应力和老化模式下的压控振荡器。

5. 发明授权

US08766680B2 Voltage translation circuit 有权
标题翻译：电压转换电路
公开(公告)号：US08766680B2
公开(公告)日：2014-07-01
申请号：US13627327
申请日：2012-09-26
申请人： Xinghai Tang , Gayathri A. Bhagavatheeswaran , Hector Sanchez
发明人： Xinghai Tang , Gayathri A. Bhagavatheeswaran , Hector Sanchez
IPC分类号： H03L7/06 , H03L5/00
CPC分类号： H03L7/0995
摘要： A voltage translation circuit (116) provides an output analog voltage signal that has a translated voltage of the voltage of an input analog voltage signal over a range of values of the input analog voltage signal. The voltage translation circuit includes an input stage (202) having a circuit node and an input transistor (210) coupled between the circuit node and a power supply terminal, wherein a gate of the input transistor is coupled to receive the input analog voltage signal; a current path circuit (204) in parallel with the input transistor, wherein the current path includes a first transistor coupled between the circuit node and the power supply terminal; and a circuit coupled to provide a variable body bias voltage to a body of the first transistor.
摘要翻译：电压转换电路（116）提供输出模拟电压信号，其在输入模拟电压信号的值的范围内具有输入模拟电压信号的电压的转换电压。电压转换电路包括具有电路节点和耦合在电路节点与电源端子之间的输入晶体管（210）的输入级（202），其中输入晶体管的栅极耦合以接收输入模拟电压信号; 与所述输入晶体管并联的电流路径电路（204），其中所述电流路径包括耦合在所述电路节点和所述电源端子之间的第一晶体管; 以及耦合以向第一晶体管的主体提供可变主体偏置电压的电路。

6. 发明申请

US20140084974A1 PHASE LOCKED LOOP WITH BURN-IN MODE 有权
标题翻译：带锁定模式的锁相环
公开(公告)号：US20140084974A1
公开(公告)日：2014-03-27
申请号：US13627333
申请日：2012-09-26
申请人： XINGHAI TANG , Gayathri A. Bhagavatheeswaran , Hector Sanchez
发明人： XINGHAI TANG , Gayathri A. Bhagavatheeswaran , Hector Sanchez
IPC分类号： H03L7/089 , H03L7/091
CPC分类号： H03L7/0891 , H03L7/0995
摘要： A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode.
摘要翻译：具有正常模式和老化模式的锁相环。逻辑部分耦合到逻辑电源端子并且包括耦合到相位频率检测器的时钟接收器。模拟部分具有耦合到相位频率检测器和模拟电源端子的电荷泵。模拟部分还具有耦合到模拟节点处的电荷泵和模拟电源端子的压控振荡器。锁相环具有在老化模式期间耦合到模拟节点的节点控制电路，其控制模拟节点处的电压足够低于模拟电源端子处的电压，以避免电荷泵的过度应力和老化模式下的压控振荡器。

7. 发明授权

US08629707B1 AC coupled level shifter 有权
标题翻译：交流耦合电平转换器
公开(公告)号：US08629707B1
公开(公告)日：2014-01-14
申请号：US13690336
申请日：2012-11-30
申请人： Hector Sanchez , Xinghai Tang , Gayathri A. Bhagavatheeswaran
发明人： Hector Sanchez , Xinghai Tang , Gayathri A. Bhagavatheeswaran
IPC分类号： H03L5/00
CPC分类号： H03K19/0175 , H03K19/0185
摘要： A level shifter includes first, second and third capacitively configured transistors, first and second switching transistors, and an inverting circuit. The first capacitively configured transistor has a first terminal that receives an input signal. Second and third capacitively configured transistor each have first terminal coupled to a second terminal of the first capacitively configured transistor. The second capacitively configured transistor is coupled in series with a first switching transistor that is also coupled to a first power supply terminal. The third capacitively configured transistor is coupled in series with a second switching transistor that is also coupled to a second power supply terminal.
摘要翻译：电平移位器包括第一，第二和第三电容配置的晶体管，第一和第二开关晶体管以及反相电路。第一电容配置晶体管具有接收输入信号的第一端子。第二和第三电容配置的晶体管每个都具有耦合到第一电容配置晶体管的第二端的第一端。第二电容配置晶体管与也耦合到第一电源端子的第一开关晶体管串联耦合。第三电容配置晶体管与第二开关晶体管串联耦合，第二开关晶体管也耦合到第二电源端子。

8. 发明申请

US20110181326A1 PHASE-LOCKED LOOP HAVING A FEEDBACK CLOCK DETECTOR CIRCUIT AND METHOD THEREFOR 有权
标题翻译：具有反馈时钟检测电路的相位锁定环路及其方法
公开(公告)号：US20110181326A1
公开(公告)日：2011-07-28
申请号：US12695461
申请日：2010-01-28
申请人： Hector Sanchez , Gayathri A. Bhagavatheeswaran , Xinghai Tang
发明人： Hector Sanchez , Gayathri A. Bhagavatheeswaran , Xinghai Tang
IPC分类号： H03L7/08
CPC分类号： H03L7/14
摘要： A method for a phase-locked loop (PLL) in an integrated circuit, wherein the PLL comprises a voltage-controlled oscillator (VCO). The method includes, in a training mode: (1) setting a control voltage of the VCO at a first voltage level; (2) increasing the control voltage of the VCO from the first voltage level to a second voltage level, until a loss of the feedback signal is detected; and (3) storing an indicator value corresponding to the second voltage level of the control voltage of the VCO. The method further includes, in a normal mode: (1) monitoring a voltage level of the control voltage of the VCO by generating a monitored indicator value corresponding to the voltage level of the control voltage of the VCO; and (2) asserting the loss of feedback signal based on a comparison of the monitored indicator value and the indicator value.
摘要翻译：一种用于集成电路中锁相环（PLL）的方法，其中PLL包括压控振荡器（VCO）。该方法包括：在训练模式中：（1）将VCO的控制电压设置在第一电压电平; （2）将VCO的控制电压从第一电压电平提高到第二电压电平，直到检测到反馈信号的损失; 和（3）存储对应于VCO的控制电压的第二电压电平的指标值。该方法还包括：在正常模式中：（1）通过产生对应于VCO的控制电压的电压电平的监视的指示值监视VCO的控制电压的电压电平; 和（2）基于所监视的指标值与指标值的比较来确定反馈信号的损失。

9. 发明授权

US08094769B2 Phase-locked loop system with a phase-error spreading circuit 有权
标题翻译：具有相位误差扩展电路的锁相环系统
公开(公告)号：US08094769B2
公开(公告)日：2012-01-10
申请号：US12180166
申请日：2008-07-25
申请人： Gayathri A. Bhagavatheeswaran , Lipeng Cao , Hector Sanchez
发明人： Gayathri A. Bhagavatheeswaran , Lipeng Cao , Hector Sanchez
IPC分类号： H03D3/24
CPC分类号： H03L7/099 , H03L7/0891 , H03L2207/06
摘要： A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses. The PLL system further includes a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses. The PLL system may also include a charge pump that generates a pumping signal based on the phase-spread pulses.
摘要翻译：提供一种锁相环（PLL）系统，其包括用于基于参考时钟和反馈时钟之间的相位差产生上行信号或下降信号的相位频率检测器。 PLL系统还包括一个相位误差扩展电路，用于根据上升信号或下降信号的第一时间属性与相位扩展脉冲的第二时间属性之间的关系产生相位扩展脉冲。 PLL系统还包括用于基于相位扩展脉冲产生VCO时钟的压控振荡器（VCO）。 PLL系统还可以包括基于相位扩展脉冲产生泵浦信号的电荷泵。

10. 发明授权

US09356577B2 Memory interface receivers having pulsed control of input signal attenuation networks 有权
标题翻译：具有脉冲控制输入信号衰减网络的存储器接口接收器
公开(公告)号：US09356577B2
公开(公告)日：2016-05-31
申请号：US14457508
申请日：2014-08-12
申请人： Hector Sanchez , Gayathri A. Bhagavatheeswaran
发明人： Hector Sanchez , Gayathri A. Bhagavatheeswaran
IPC分类号： H03L5/00 , H03H11/24 , G11C11/4093 , H03K5/08
CPC分类号： H03H11/24 , G11C7/1084 , G11C11/4093 , H03H7/24 , H03K5/084
摘要： Receivers for memory interfaces and related methods are disclosed having pulsed control of input signal attenuation networks. Embodiments include a DC common mode attenuation network, an AC coupling network, a pulse generator, and an amplifier. The pulse generator receives the output of the amplifier and generates a pulse signal that in part controls the operation of the attenuation network. The attenuation network generates an attenuated signal having reduced DC common mode levels. This attenuated signal is combined with an AC component passed by the AC coupling network. The resulting combined signal is detected and amplified by the amplifier. Different voltage domains are used for the attenuation network and the AC coupling network as compared to the amplifier and the pulse generator. By attenuating DC common mode levels while maintaining AC signal levels, the disclosed embodiments allow for proper signal detection over a wide range of DC common mode levels.
摘要翻译：公开了用于存储器接口和相关方法的接收机，其具有输入信号衰减网络的脉冲控制。实施例包括DC共模衰减网络，AC耦合网络，脉冲发生器和放大器。脉冲发生器接收放大器的输出并产生部分地控制衰减网络的操作的脉冲信号。衰减网络产生具有降低的DC共模电平的衰减信号。该衰减信号与由AC耦合网络传递的AC分量组合。所得到的组合信号由放大器检测和放大。与放大器和脉冲发生器相比，不同的电压域用于衰减网络和AC耦合网络。通过在维持AC信号电平的同时衰减DC共模电平，所公开的实施例允许在宽范围的DC共模电平上进行适当的信号检测。

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