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1. 发明授权

US07412681B1 DC path checking in a hierarchical circuit design 失效
标题翻译： DC路径检查在分层电路设计中
公开(公告)号：US07412681B1
公开(公告)日：2008-08-12
申请号：US11067571
申请日：2005-02-25
申请人： Xiaodong Zhang , Jun Kong , Bruce W. McGaughy
发明人： Xiaodong Zhang , Jun Kong , Bruce W. McGaughy
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer implemented method is provided for use in evaluating a hierarchical representation of a circuit design encoded in a computer readable medium comprising: traversing a circuit path within a higher level circuit that includes a reference potential connection, to identify a port of a call to a first lower level circuit that is DC path connected to the reference potential; identifying a first DC port group that includes each port of the call to the first lower level circuit that is DC path connected to the identified port of the call to the first lower level circuit; automatically marking as DC path connected to the reference potential, each port of the call to the first lower level circuit that is a member of the first DC port group; and traversing a circuit path within the first lower level circuit to identify a circuit path within the first lower level circuit that is DC path connected to a marked port of the first lower level circuit.
摘要翻译：提供了一种用于评估在计算机可读介质中编码的电路设计的分层表示的计算机实现的方法，包括：遍历包括参考电位连接的更高级电路内的电路路径，以识别对第一低电平电路，其是连接到参考电位的DC路径; 识别包括与所述第一下层电路的呼叫的每个端口的第一DC端口组，所述第一下层电路是连接到所识别的对所述第一下级电路的呼叫端口的DC路径; 自动标记为连接到参考电位的DC路径，调用作为第一DC端口组成员的第一下层电路的每个端口; 并且穿过第一下层电路内的电路，以识别第一下层电路内的电路路径，该路径是连接到第一下层电路的标记端口的DC路径。

2. 发明授权

US08255856B1 DC path checking in a hierarchical circuit design 失效
标题翻译： DC路径检查在分层电路设计中
公开(公告)号：US08255856B1
公开(公告)日：2012-08-28
申请号：US12189645
申请日：2008-08-11
申请人： Xiaodong Zhang , Jun Kong , Bruce W. McGaughy
发明人： Xiaodong Zhang , Jun Kong , Bruce W. McGaughy
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer implemented method is provided for use in evaluating a hierarchical representation of a circuit design encoded in a computer readable medium comprising: traversing a circuit path within a higher level circuit that includes a reference potential connection, to identify a port of a call to a first lower level circuit that is DC path connected to the reference potential; identifying a first DC port group that includes each port of the call to the first lower level circuit that is DC path connected to the identified port of the call to the first lower level circuit; automatically marking as DC path connected to the reference potential, each port of the call to the first lower level circuit that is a member of the first DC port group; and traversing a circuit path within the first lower level circuit to identify a circuit path within the first lower level circuit that is DC path connected to a marked port of the first lower level circuit.
摘要翻译：提供了一种用于评估在计算机可读介质中编码的电路设计的分层表示的计算机实现的方法，包括：遍历包括参考电位连接的更高级电路内的电路路径，以识别对第一低电平电路，其是连接到参考电位的DC路径; 识别包括与所述第一下层电路的呼叫的每个端口的第一DC端口组，所述第一下层电路是连接到所识别的对所述第一下级电路的呼叫端口的DC路径; 自动标记为连接到参考电位的DC路径，调用作为第一DC端口组成员的第一下层电路的每个端口; 并且穿过第一下层电路内的电路，以识别第一下层电路内的电路路径，该路径是连接到第一下层电路的标记端口的DC路径。

3. 发明授权

US07409328B1 System and method for communicating simulation solutions between circuit components in a hierarchical data structure 失效
标题翻译：用于在分层数据结构中的电路组件之间传递模拟解决方案的系统和方法
公开(公告)号：US07409328B1
公开(公告)日：2008-08-05
申请号：US10713754
申请日：2003-11-13
申请人： Bruce W. McGaughy , Jun Kong , Peter Frey , Jaideep Muhkerjee
发明人： Bruce W. McGaughy , Jun Kong , Peter Frey , Jaideep Muhkerjee
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system for communicating simulation solutions between circuit components in a hierarchical data structure includes a simulator module having one or more computer programs for representing the circuit as a hierarchically arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically arranged set of branches includes a first branch that contains one or more driver leaf circuits and a second branch that also contains one or more receiver leaf circuits, where the first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches. The simulator module further includes computer programs for simulating operation of the one or more driver leaf circuits and the one or more receiver leaf circuits, together, without simulating operation of the third branch to determine a first set of changes in signal conditions shared by the one or more driver leaf circuits and the one or more receiver leaf circuits.
摘要翻译：用于在分层数据结构中的电路组件之间传递模拟解决方案的系统包括具有一个或多个计算机程序的模拟器模块，该计算机程序用于将该电路表示为分层布置的分支集，其包括根分支和逻辑上组织在一起的多个其他分支一张图。分层布置的分支集合包括包含一个或多个驱动器叶电路的第一分支和还包含一个或多个接收器叶电路的第二分支，其中第一分支和第二分支通过第三分支在图中互连，图中的分级水平高于第一和第二分支。模拟器模块还包括用于在不模拟第三分支的操作的情况下模拟一个或多个驱动器叶电路和一个或多个接收器叶电路的操作的计算机程序，以确定由该一个共享的信号条件的第一组变化或更多的驱动器叶电路和一个或多个接收器叶电路。

4. 发明授权

US08326591B1 Synchronized envelope and transient simulation of circuits 有权
标题翻译：电路的同步包络和瞬态仿真
公开(公告)号：US08326591B1
公开(公告)日：2012-12-04
申请号：US11941904
申请日：2007-11-16
申请人： Qian Cai , Dan Feng , Bruce W. McGaughy , Jun Kong , Rendong Lin
发明人： Qian Cai , Dan Feng , Bruce W. McGaughy , Jun Kong , Rendong Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In one embodiment of the invention, a method of simulating a circuit is disclosed including partitioning a circuit into a plurality of blocks, each of the plurality of blocks being radio-frequency blocks or non-radio frequency blocks; performing a first simulation of a first simulation type with the radio-frequency blocks to generate output waveforms of the radio-frequency blocks; performing a second simulation of a second simulation type with the non-radio-frequency blocks to generate output waveforms of the non-radio-frequency blocks where the second simulation type differs from the first simulation type; and synchronizing the first simulation and the second simulation together at one or more time steps to generate output waveforms for the circuit.
摘要翻译：在本发明的一个实施例中，公开了一种模拟电路的方法，包括将电路划分成多个块，所述多个块中的每一个是射频块或非射频块; 利用所述射频块执行第一仿真类型的第一仿真以产生所述射频块的输出波形; 对非射频块进行第二仿真类型的第二仿真，以产生第二仿真类型与第一仿真类型不同的非射频块的输出波形; 以及在一个或多个时间步骤一起同步所述第一仿真和所述第二仿真以产生所述电路的输出波形。

5. 发明授权

US07836419B1 Method and system for partitioning integrated circuits 有权
标题翻译：集成电路分区方法和系统
公开(公告)号：US07836419B1
公开(公告)日：2010-11-16
申请号：US11390574
申请日：2006-03-27
申请人： Bruce W. McGaughy , Jun Kong
发明人： Bruce W. McGaughy , Jun Kong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Method and system for partitioning integrated circuits are disclosed. The method includes receiving a netlist representation of the circuit comprising circuit components, partitioning the circuit to form one or more circuit partitions according to a predefined partitioning method, where each circuit partition includes one or more circuit components. The method further includes, for each circuit partition, identifying substantial correlations between the circuit partition and one or more other circuit partitions to form a spanning tree, where the spanning tree connects the circuit partition to the one or more other circuit partitions via a graph, and merging the circuit partition and the one or more other circuit partitions in the spanning tree to form a new circuit partition.
摘要翻译：公开了用于划分集成电路的方法和系统。该方法包括接收包括电路组件的电路的网表表示，根据预定义的分区方法划分电路以形成一个或多个电路分区，其中每个电路分区包括一个或多个电路组件。该方法还包括对于每个电路分区，识别电路分区与一个或多个其他电路分区之间的实质相关性以形成生成树，其中生成树通过图形将电路分区连接到一个或多个其他电路分区，并将电路分区和生成树中的一个或多个其他电路分区合并以形成新的电路分区。

6. 发明授权

US07434183B2 Method and system for validating a hierarchical simulation database 失效
标题翻译：验证分层仿真数据库的方法和系统
公开(公告)号：US07434183B2
公开(公告)日：2008-10-07
申请号：US11206714
申请日：2005-08-17
申请人： Bruce W. McGaughy , Jun Kong
发明人： Bruce W. McGaughy , Jun Kong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/504
摘要： System and method for validating a circuit for simulation are disclosed. The system includes at least one processing unit for executing computer programs, a graphical user interface for viewing representations of the circuit on a display, a memory for storing information of the circuit, and logic for representing the circuit in a hierarchical data structure, where the hierarchical data structure has a plurality of subcircuits arranged in a connected graph, and where each subcircuit has circuit elements and one or more input and output ports. The system further includes logic for traversing the hierarchical data structure in a bottom-up fashion, logic for recording input port to output port (port-to-port) properties of the subcircuits in the hierarchical data structure, logic for traversing the hierarchical data structure in a top-down fashion, and logic for identifying illegal port paths using the port-to-port properties of the subcircuits.
摘要翻译：公开了用于验证用于模拟的电路的系统和方法。该系统包括用于执行计算机程序的至少一个处理单元，用于查看显示器上的电路的表示的图形用户界面，用于存储电路的信息的存储器和用于以分层数据结构表示电路的逻辑，其中分层数据结构具有布置在连接图中的多个子电路，并且其中每个子电路具有电路元件和一个或多个输入和输出端口。该系统还包括用于以自下而上的方式遍历分层数据结构的逻辑，用于将输入端口记录到分级数据结构中的子电路的输出端口（端口到端口）特性的逻辑，用于遍历分层数据结构的逻辑以自顶向下的方式，以及使用子电路的端口到端口属性来识别非法端口路径的逻辑。

7. 发明授权

US07243313B1 System and method for reducing the size of RC circuits 有权
标题翻译：减小RC电路尺寸的系统和方法
公开(公告)号：US07243313B1
公开(公告)日：2007-07-10
申请号：US10721673
申请日：2003-11-24
申请人： Wangguo Qin , Bruce W. McGaughy , Jun Kong , Qingjian Yu
发明人： Wangguo Qin , Bruce W. McGaughy , Jun Kong , Qingjian Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of transforming a first topology to a reduced topology is disclosed. One preferred embodiment of the present invention includes a method of transforming a circuit from a first topology to a reduced topology, said first topology comprising a plurality of inter-connected circuit elements. The method comprises the steps of: (a) identifying one or more circuit elements; (b) analyzing the effect of reducing one or more of said identified circuit elements on the topological and physical characteristics of said circuit; and (c) if the effect satisfies a first standard, generating a second topology reflecting the reduction of one or more identified circuit elements.
摘要翻译：公开了将第一拓扑转换为简化拓扑的方法。本发明的一个优选实施例包括一种将电路从第一拓扑转换为简化拓扑的方法，所述第一拓扑包括多个互连电路元件。该方法包括以下步骤：（a）识别一个或多个电路元件; （b）分析减少所述识别的电路元件中的一个或多个对所述电路的拓扑和物理特性的影响; 以及（c）如果所述效果满足第一标准，则产生反映一个或多个所识别的电路元件的减少的第二拓扑。

8. 发明授权

US07392170B1 System and method for dynamically compressing circuit components during simulation 有权
标题翻译：仿真期间动态压缩电路元件的系统和方法
公开(公告)号：US07392170B1
公开(公告)日：2008-06-24
申请号：US10713729
申请日：2003-11-13
申请人： Bruce W. McGaughy , Jun Kong
发明人： Bruce W. McGaughy , Jun Kong
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system for dynamically compressing circuit components during simulating of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) selecting a group of leaf circuits from the first and second branches for simulation, 2) if two or more leaf circuits of the circuit having a substantially same isomorphic behavior, representing the two or more leaf circuits as a merged leaf circuit, 3) creating a first port connectivity interface dynamically for the group of leaf circuits in response to the merged leaf circuit, where the first port connectivity interface communicates changes in signal conditions among the group of leaf circuits, and 4) simulating the group of leaf circuits in accordance with the first port connectivity interface. Since the system dynamically compresses two or more leaf circuits which demonstrate substantially same isomorphic behavior into a merged leaf circuit, there are less number of circuits in the dynamic database and less number of computations are performed during simulation. Therefore, the system uses less memory and achieves higher simulation performance.
摘要翻译：一种用于在具有分层数据结构的电路的仿真期间动态压缩电路组件的系统包括具有一个或多个计算机程序的模拟器模块，用于1）从第一和第二分支中选择一组叶电路进行模拟，2）如果两个或所述电路的更多叶片电路具有基本上相同的同构行为，表示作为合并叶片电路的两个或多个叶片电路，3）响应于合并叶片电路为该组叶片电路动态地创建第一端口连接接口，其中第一端口连接接口在叶片电路组之间传送信号条件的变化，以及4）根据第一端口连接接口模拟叶片电路组。由于系统动态地压缩两个或更多个叶片电路，它们将合成叶片电路中具有基本相同的同构行为，所以动态数据库中的电路数量较少，在仿真过程中执行的计算次数较少。因此，系统使用更少的内存并实现更高的仿真性能。

9. 发明授权

US07269541B1 System and method for supporting multi-rate simulation of a circuit having hierarchical data structure 有权
标题翻译：支持具有分层数据结构的电路的多速率仿真的系统和方法
公开(公告)号：US07269541B1
公开(公告)日：2007-09-11
申请号：US10713753
申请日：2003-11-13
申请人： Bruce W. McGaughy , Peter Frey , Jun Kong , Baolin Yang
发明人： Bruce W. McGaughy , Peter Frey , Jun Kong , Baolin Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system for supporting multi-rate simulation of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) partitioning the circuit into a plurality of group circuits, each group circuit includes one or more leaf circuits, where each leaf circuit produces a predictable set of output signals with a given set of input signals, 2) storing the group circuits in a scheduled event queue in accordance with priority in time which the group circuits need to be simulated, 3) retrieving from the scheduled event queue a set of group circuits for simulation within a predetermined time period, 4) distributing the set of group circuits into a set of predefined event lists, where each of the predefined event list stores one or more group circuits of a corresponding event type, and 5) simulating the one or more group circuits in each of the predefined event list in accordance with a rate of change of signal conditions of each individual group circuit. Hence, the system provides an efficient way to support multi-rate simulation by dynamically scheduling and synchronizing multiple group simulation event types and by communicating corresponding isomorphic activities through an efficient port connectivity interface.
摘要翻译：一种用于支持具有分层数据结构的电路的多速率仿真的系统包括具有一个或多个计算机程序的模拟器模块，用于1）将电路划分为多个组电路，每个组电路包括一个或多个叶电路，其中每个叶片电路产生具有给定的一组输入信号的可预测的一组输出信号，2）根据组电路需要模拟的时间优先级将组电路存储在调度事件队列中; 3）从调度的事件队列一组用于在预定时间段内进行模拟的组电路，4）将所述组电路组分配成一组预定事件列表，其中每个预定事件列表存储相应事件类型的一个或多个组电路，以及5）根据每个单独组的信号条件的变化率来模拟每个预定事件列表中的一个或多个组电路电路。因此，该系统通过动态调度和同步多组模拟事件类型并通过有效的端口连接接口传达相应的同构活动来提供有效的方式来支持多速率模拟。

10. 发明授权

US07181383B1 System and method for simulating a circuit having hierarchical structure 有权
标题翻译：用于模拟具有分层结构的电路的系统和方法
公开(公告)号：US07181383B1
公开(公告)日：2007-02-20
申请号：US10724277
申请日：2003-11-26
申请人： Bruce W. McGaughy , Prashant Karhade , Jaideep Muhkerjee , Jun Kong
发明人： Bruce W. McGaughy , Prashant Karhade , Jaideep Muhkerjee , Jun Kong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system for simulating a circuit having hierarchical data structure includes a simulator module having one or more computer programs for 1) creating a static database in accordance with a netlist description of the circuit, where the static database contains topology information of the circuit; 2) selecting a group circuit for simulation, where the group circuit contains one or more leaf circuits selected from the first branch and the second branch; 3) creating a dynamic database for representing the group circuit, where the dynamic database includes references to the static database for fetching topology information dynamically during simulation; and 4) simulating the group circuit in accordance with the dynamic database. Since the system duplicates and reproduces only the relevant dynamic information when necessary, the disclosed circuit simulator uses less memory and produces better performance.
摘要翻译：一种用于模拟具有分层数据结构的电路的系统，包括具有一个或多个计算机程序的模拟器模块，用于1）根据电路的网表描述创建静态数据库，其中静态数据库包含电路的拓扑信息; 2）选择用于模拟的组电路，其中组电路包含从第一分支和第二分支选择的一个或多个叶子电路; 3）创建用于表示组电路的动态数据库，其中动态数据库包括对静态数据库的引用，用于在模拟期间动态地获取拓扑信息; 和4）根据动态数据库模拟组电路。由于该系统在必要时仅复制并再现相关的动态信息，因此所公开的电路模拟器使用较少的存储器并产生更好的性能。

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