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1. 发明授权

US06794262B2 MIM capacitor structures and fabrication methods in dual-damascene structures 失效
公开(公告)号：US06794262B2
公开(公告)日：2004-09-21
申请号：US10252476
申请日：2002-09-23
申请人： Xian J. Ning , Keith Kwong Hon Wong
发明人： Xian J. Ning , Keith Kwong Hon Wong
IPC分类号： H01L2120
CPC分类号： H01L28/86 , H01L21/31604 , H01L21/76807 , H01L23/5223 , H01L28/55 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor (242/252) structure and method of forming the same. A dielectric layer (214) of a semiconductor device (200) is patterned with a dual damascene pattern having a first pattern (216) and a second pattern (218). The second pattern (218) has a greater depth than the first pattern (216). A conductive layer (226) is formed over the dielectric layer (214) in the first pattern, and a conductive layer is formed over the conductive layer in the first pattern (216). A dielectric layer (232), conductive layer (234), dielectric layer (236) and conductive layer (238) are disposed over the conductive layer (226) of the second pattern (218). Conductive layer (234), dielectric layer (232) and conductive layer (226) form a first MIM capacitor (252). Conductive layer (238), dielectric layer (236) and conductive layer (234) form a second MIM capacitor (242) parallel to the first MIM capacitor (242).

2. 发明授权

US06750115B1 Method for generating alignment marks for manufacturing MIM capacitors 失效
标题翻译：用于产生用于制造MIM电容器的对准标记的方法
公开(公告)号：US06750115B1
公开(公告)日：2004-06-15
申请号：US10303462
申请日：2002-11-25
申请人： Xian J. Ning , Keith Kwong Hon Wong
发明人： Xian J. Ning , Keith Kwong Hon Wong
IPC分类号： H01I218242
CPC分类号： H01L28/40 , H01L23/544 , H01L27/0805 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device, comprising depositing an insulating layer over a workpiece, and defining a pattern for at least one alignment marks, at least one MIM capacitor, and a plurality of conductive lines within the insulating layer. A resist is formed over the alignment marks and MIM capacitor pattern, and a conductive material is deposited over the wafer to fill the conductive pattern. The wafer is chemically-mechanically polished to remove excess conductive material from over the insulating layer and form conductive lines. The resist is removed from over the alignment mark and MIM capacitor pattern. MIM capacitor material layers are deposited over the wafer, and the wafer is chemically-mechanically polished to form a MIM capacitor, while leaving the topography of the alignment marks visible on the surface of the wafer, so that the alignment marks may be used for alignment of subsequently deposited layers of the semiconductor device.
摘要翻译：一种制造半导体器件的方法，包括在工件上沉积绝缘层，并且限定用于至少一个对准标记的图案，至少一个MIM电容器和绝缘层内的多条导电线。在对准标记和MIM电容器图案上形成抗蚀剂，并且在晶片上沉积导电材料以填充导电图案。晶片被化学机械抛光以从绝缘层上方去除多余的导电材料并形成导电线。从对准标记和MIM电容器图案上去除抗蚀剂。将MIM电容器材料层沉积在晶片上，并且晶片被化学机械抛光以形成MIM电容器，同时留下在晶片表面上可见的对准标记的形貌，使得对准标记可用于对准的后续沉积的半导体器件的层。

3. 发明授权

US08158520B2 Method of forming a via structure dual damascene structure for the manufacture of semiconductor integrated circuit devices 有权
标题翻译：形成用于制造半导体集成电路器件的通孔结构双镶嵌结构的方法
公开(公告)号：US08158520B2
公开(公告)日：2012-04-17
申请号：US10969886
申请日：2004-10-20
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76807 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit device structure with a novel contact feature. The structure includes a substrate, a dielectric layer overlying the substrate, and a metal interconnect overlying the dielectric layer. A first interlayer dielectric layer is formed surrounding the metal interconnect. A second interlayer dielectric layer of a predetermined thickness is overlying the first interlayer dielectric layer. A trench opening of a first width is formed within an upper portion of the second interlayer dielectric layer. A first barrier layer is within and is overlying the trench opening of the first width. A contact opening of a second width is within a lower portion of the second interlayer dielectric layer. The second width is less than the first width. The lower portion of the second interlayer dielectric layer is coupled to the upper portion of the second interlayer dielectric layer within the predetermined thickness of the second interlayer dielectric. A second barrier layer is within and is overlying the opening of the contact opening and overlying the first barrier layer. A directional partially or completely removal of the second barrier forming a low contact resistance structure. A copper material is formed overlying the first barrier layer and the second barrier layer to substantially fill the contact opening and the trench within the second interlayer dielectric layer.
摘要翻译：具有新颖接触特征的集成电路器件结构。该结构包括衬底，覆盖衬底的电介质层和覆盖在电介质层上的金属互连。形成围绕金属互连的第一层间介质层。具有预定厚度的第二层间介质层覆盖在第一层间介电层上。在第二层间电介质层的上部形成有第一宽度的沟槽开口。第一阻挡层位于第一宽度的沟槽开口内并且覆盖第一宽度的沟槽开口。第二宽度的接触开口在第二层间电介质层的下部内。第二宽度小于第一宽度。第二层间电介质层的下部在第二层间电介质的预定厚度内耦合到第二层间电介质层的上部。第二阻挡层位于接触开口的开口内并且覆盖在第一阻挡层上方。定向部分地或完全地去除形成低接触电阻结构的第二阻挡层。形成覆盖在第一阻挡层和第二阻挡层上的铜材料，以基本上填充第二层间电介质层内的接触开口和沟槽。

4. 发明授权

US07479699B2 Seal ring structures with unlanded via stacks 有权
标题翻译：密封环结构，带有无底板的堆叠
公开(公告)号：US07479699B2
公开(公告)日：2009-01-20
申请号：US11611391
申请日：2006-12-15
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L23/48
CPC分类号： H01L23/585 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： Techniques for an integrated circuit device are provided. The integrated circuit device includes a semiconductor substrate, an integrated circuit, a dielectric layer, and a sealing structure. The sealing structure surrounds the integrated circuit and is disposed within the dielectric layer to prevent damage to the integrated circuit. The sealing structure includes a plurality of metal traces organized in vertical layers and a plurality of vias. Each via of the plurality of vias couples at least two metal traces of the plurality of metal traces from adjacent vertical layers. Each via of the plurality of vias contacts at least two orthogonal surfaces of a lower metal trace of the at least two metal traces. The plurality of metal traces and plurality of vias form a continuous boundary.
摘要翻译：提供了一种用于集成电路器件的技术。集成电路器件包括半导体衬底，集成电路，电介质层和密封结构。密封结构围绕集成电路并且设置在介电层内以防止对集成电路的损坏。密封结构包括以垂直层和多个通孔组织的多个金属迹线。多个通孔的每个通孔将多个金属迹线中的至少两个金属迹线与相邻的垂直层耦合。多个通孔的每个通孔接触至少两个金属迹线的下部金属迹线的至少两个正交表面。多个金属迹线和多个通孔形成连续的边界。

5. 发明申请

US20080142975A1 DUMMY PATTERNS AND METHOD OF MANUFACTURE FOR MECHANICAL STRENGTH OF LOW K DIELECTRIC MATERIALS IN COPPER INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DEVICES 有权
标题翻译：低介电材料的机械强度的制造方法和制造方法在半导体器件的铜互连结构中
公开(公告)号：US20080142975A1
公开(公告)日：2008-06-19
申请号：US11611332
申请日：2006-12-15
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76801 , H01L23/522 , H01L23/53228 , H01L24/03 , H01L24/05 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A method for fabricating a semiconductor device. The method includes providing a semiconductor substrate including a surface region. The method forms a first interlayer dielectric overlying the surface region and forms an interconnect layer overlying the first interlayer dielectric layer. The method also forms a low K dielectric layer overlying the interconnect layer, which has a predetermined shape. The method forms a copper interconnect layer overlying the low K dielectric layer. In a preferred embodiment, the low K dielectric layer maintains the predetermined shape using a dummy pattern structure provided within a portion of the low K dielectric layer to mechanically support and maintain the predetermined shape of the low K dielectric layer between the interconnect layer and the copper interconnect layer.
摘要翻译：一种半导体器件的制造方法。该方法包括提供包括表面区域的半导体衬底。该方法形成覆盖表面区域的第一层间电介质，并形成覆盖第一层间介质层的互连层。该方法还形成了覆盖互连层的低K电介质层，其具有预定的形状。该方法形成覆盖在低K电介质层上的铜互连层。在优选实施例中，低K电介质层使用设置在低K电介质层的一部分内的虚设图案结构来保持预定形状，以在互连层和铜之间机械地支撑和保持低K电介质层的预定形状互连层。

6. 发明授权

US06979526B2 Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs 失效
标题翻译：用于MRAM的抗蚀剂掩模阻挡形成的平版印刷对准和覆盖测量标记
公开(公告)号：US06979526B2
公开(公告)日：2005-12-27
申请号：US10161867
申请日：2002-06-03
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： G03F7/20 , G03F9/00 , G03F7/40 , H01L21/00 , H01L21/20 , H01L21/311
CPC分类号： G03F9/708 , G03F7/70633 , G03F9/7084 , H01L27/222 , H01L43/12
摘要： A method of manufacturing a resistive semiconductor memory device (10), comprising depositing an insulating layer (34) over a workpiece (30), and defining a pattern for a plurality of alignment marks (22) and a plurality of conductive lines (54) within the insulating layer (34). A resist (50) is formed over the alignment marks (22), and a conductive material (52) is deposited over the wafer to fill the conductive pattern. The wafer is chemically-mechanically polished to remove excess conductive material from over the insulating layer and form conductive lines (54). The resist (50) is removed from over the alignment marks (22), and the alignment marks (22) are used for alignment of subsequently deposited layers of the resistive memory device (10).
摘要翻译：一种制造电阻半导体存储器件（10）的方法，包括在工件（30）上沉积绝缘层（34），并且限定多个对准标记（22）和多条导线（54）的图案，在绝缘层（34）内。在对准标记（22）之上形成抗蚀剂（50），并且导电材料（52）沉积在晶片上以填充导电图案。晶片被化学机械抛光以从绝缘层上方去除多余的导电材料并形成导电线（54）。从对准标记（22）上方去除抗蚀剂（50），并且对准标记（22）用于电阻式存储器件（10）的后续沉积层的对准。

7. 发明授权

US06960365B2 Vertical MIMCap manufacturing method 失效
标题翻译：垂直MIMCap制造方法
公开(公告)号：US06960365B2
公开(公告)日：2005-11-01
申请号：US10057575
申请日：2002-01-25
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L21/02 , H01L27/08 , B05D5/12 , H01L21/20 , H01L29/00
CPC分类号： H01L28/60 , H01L27/0805 , H01L28/55 , H01L28/75 , H01L28/91
摘要： A method of manufacturing a vertical metal-insulator-metal capacitor (MIMCap) (10) in regions (19) of an insulating layer (14). Trenches for both conductive lines and vertical MIMCap's are formed in the insulating layer (14), and regions (19) are covered by resist (20) while the conductive lines (24) are deposited on the wafer. The resist (20) is removed, and the MIMCap dielectric and top plate conductive material (28) is deposited, forming a vertical MIMCap in regions (19).
摘要翻译：一种在绝缘层（14）的区域（19）中制造垂直金属 - 绝缘体 - 金属电容器（MIMCap）（10）的方法。在绝缘层（14）中形成用于导电线和垂直MIMCap的沟槽，并且当导电线（24）沉积在晶片上时，区域（19）被抗蚀剂（20）覆盖。去除抗蚀剂（20），并且沉积MIMCap电介质和顶板导电材料（28），在区域（19）中形成垂直MIMCap。

8. 发明授权

US06635496B2 Plate-through hard mask for MRAM devices 有权
标题翻译：用于MRAM设备的平板硬掩模
公开(公告)号：US06635496B2
公开(公告)日：2003-10-21
申请号：US09977027
申请日：2001-10-12
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L2100
CPC分类号： H01L27/222 , H01L43/12
摘要： A method of fabricating an MRAM device includes patterning a magnetic stack material layer (142) using a herd mask (146) formed by a “plate-through” technique. A resist (144) is deposited over magnetic stack material (142), and the resist (144) is patterned, exposing regions of the magnetic stack material (142). A hard mask (146) is formed over the magnetic stack material (142) exposed regions through the resist (144), and the hard mask (146) is used to pattern magnetic tunnel junctions (MTJ's) of the MRAM device. Electroplating, electro-less plating, sputtering, physical vapor deposition (PVD), evaporation deposition, or combinations thereof are used to deposit a material comprising a metal over the magnetic stack material (142) exposed regions to form the hard mask (146).
摘要翻译：一种制造MRAM器件的方法包括使用由“平板”技术形成的群体掩模（146）图案化磁性堆叠材料层（142）。抗蚀剂（144）沉积在磁性堆叠材料（142）上，并且对抗蚀剂（144）进行图案化，暴露磁性堆叠材料（142）的区域。在磁性堆叠材料（142）上形成通过抗蚀剂（144）的暴露区域的硬掩模（146），并且硬掩模（146）用于对MRAM器件的磁性隧道结（MTJ）进行图案化。使用电镀，无电镀，溅射，物理气相沉积（PVD），蒸发沉积或其组合以将包含金属的材料沉积在磁性堆叠材料（142）暴露区域上以形成硬掩模（146）。

9. 发明授权

US07820500B2 Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained silicon 有权
标题翻译：使用应变硅集成PMOS和NMOS晶体管的单掩模方案和结构
公开(公告)号：US07820500B2
公开(公告)日：2010-10-26
申请号：US11471071
申请日：2006-06-19
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for forming a CMOS integrated circuit using strained silicon technology. The method forms a liner layer overlying the first gate structure and the second gate structure and overlying first source/drain regions in the first well region and second source/drain regions in the second well region. In a preferred embodiment, the method patterns A spacer dielectric layer to form first sidewall spacer structures on the first gate structure, including the first edges and to form the second sidewall spacer structures on the second gate structure, including the second edges, while using a portion of the liner layer as a stop layer. The method maintains the liner layer overlying the first source/drain regions and second source/drain regions during at least the patterning of the spacer dielectric layer according to a preferred embodiment. The method also etches a first source region and a first drain region adjacent to the first gate structure using the hard mask layer and the first sidewall spacers as a protective layer. The method deposits a silicon germanium fill material into the first source region and the first drain region to fill the etched first source region and the etched first drain region while causing the first channel region between the first source region and the first drain region to be strained in compressive mode from at least the silicon germanium material formed in the first source region and the first drain region.
摘要翻译：一种使用应变硅技术形成CMOS集成电路的方法。该方法形成覆盖第一栅极结构和第二栅极结构并覆盖第一阱区中的第一源极/漏极区域和第二阱区域中的第二源极/漏极区域的衬底层。在优选实施例中，方法图案A间隔电介质层，以在第一栅极结构上形成第一侧壁间隔结构，包括第一边缘并且在第二栅极结构上形成包括第二边缘的第二侧壁间隔结构，同时使用衬垫层的一部分作为停止层。根据优选实施例，该方法在至少图案化间隔电介质层期间保持覆盖第一源极/漏极区域和第二源极/漏极区域的衬底层。该方法还使用硬掩模层和第一侧壁间隔物作为保护层来蚀刻与第一栅极结构相邻的第一源极区域和第一漏极区域。该方法将硅锗填充材料沉积到第一源极区域和第一漏极区域中以填充蚀刻的第一源极区域和蚀刻的第一漏极区域，同时使第一源极区域和第一漏极区域之间的第一沟道区域变得紧张至少在形成于第一源极区域和第一漏极区域中的硅锗材料的压缩模式。

10. 发明授权

US07605470B2 Dummy patterns and method of manufacture for mechanical strength of low K dielectric materials in copper interconnect structures for semiconductor devices 有权
标题翻译：用于半导体器件的铜互连结构中的低K电介质材料的机械强度的虚拟图案和制造方法
公开(公告)号：US07605470B2
公开(公告)日：2009-10-20
申请号：US11611332
申请日：2006-12-15
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L23/48
CPC分类号： H01L21/76801 , H01L23/522 , H01L23/53228 , H01L24/03 , H01L24/05 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A method for fabricating a semiconductor device. The method includes providing a semiconductor substrate including a surface region. The method forms a first interlayer dielectric overlying the surface region and forms an interconnect layer overlying the first interlayer dielectric layer. The method also forms a low K dielectric layer overlying the interconnect layer, which has a predetermined shape. The method forms a copper interconnect layer overlying the low K dielectric layer. In a preferred embodiment, the low K dielectric layer maintains the predetermined shape using a dummy pattern structure provided within a portion of the low K dielectric layer to mechanically support and maintain the predetermined shape of the low K dielectric layer between the interconnect layer and the copper interconnect layer.
摘要翻译：一种半导体器件的制造方法。该方法包括提供包括表面区域的半导体衬底。该方法形成覆盖表面区域的第一层间电介质，并形成覆盖第一层间介质层的互连层。该方法还形成了覆盖互连层的低K电介质层，其具有预定的形状。该方法形成覆盖在低K电介质层上的铜互连层。在优选实施例中，低K电介质层使用设置在低K电介质层的一部分内的虚设图案结构来保持预定形状，以在互连层和铜之间机械地支撑和保持低K电介质层的预定形状互连层。

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