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1. 发明授权

US07820500B2 Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained silicon 有权
标题翻译：使用应变硅集成PMOS和NMOS晶体管的单掩模方案和结构
公开(公告)号：US07820500B2
公开(公告)日：2010-10-26
申请号：US11471071
申请日：2006-06-19
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for forming a CMOS integrated circuit using strained silicon technology. The method forms a liner layer overlying the first gate structure and the second gate structure and overlying first source/drain regions in the first well region and second source/drain regions in the second well region. In a preferred embodiment, the method patterns A spacer dielectric layer to form first sidewall spacer structures on the first gate structure, including the first edges and to form the second sidewall spacer structures on the second gate structure, including the second edges, while using a portion of the liner layer as a stop layer. The method maintains the liner layer overlying the first source/drain regions and second source/drain regions during at least the patterning of the spacer dielectric layer according to a preferred embodiment. The method also etches a first source region and a first drain region adjacent to the first gate structure using the hard mask layer and the first sidewall spacers as a protective layer. The method deposits a silicon germanium fill material into the first source region and the first drain region to fill the etched first source region and the etched first drain region while causing the first channel region between the first source region and the first drain region to be strained in compressive mode from at least the silicon germanium material formed in the first source region and the first drain region.
摘要翻译：一种使用应变硅技术形成CMOS集成电路的方法。该方法形成覆盖第一栅极结构和第二栅极结构并覆盖第一阱区中的第一源极/漏极区域和第二阱区域中的第二源极/漏极区域的衬底层。在优选实施例中，方法图案A间隔电介质层，以在第一栅极结构上形成第一侧壁间隔结构，包括第一边缘并且在第二栅极结构上形成包括第二边缘的第二侧壁间隔结构，同时使用衬垫层的一部分作为停止层。根据优选实施例，该方法在至少图案化间隔电介质层期间保持覆盖第一源极/漏极区域和第二源极/漏极区域的衬底层。该方法还使用硬掩模层和第一侧壁间隔物作为保护层来蚀刻与第一栅极结构相邻的第一源极区域和第一漏极区域。该方法将硅锗填充材料沉积到第一源极区域和第一漏极区域中以填充蚀刻的第一源极区域和蚀刻的第一漏极区域，同时使第一源极区域和第一漏极区域之间的第一沟道区域变得紧张至少在形成于第一源极区域和第一漏极区域中的硅锗材料的压缩模式。

2. 发明授权

US07605470B2 Dummy patterns and method of manufacture for mechanical strength of low K dielectric materials in copper interconnect structures for semiconductor devices 有权
标题翻译：用于半导体器件的铜互连结构中的低K电介质材料的机械强度的虚拟图案和制造方法
公开(公告)号：US07605470B2
公开(公告)日：2009-10-20
申请号：US11611332
申请日：2006-12-15
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L23/48
CPC分类号： H01L21/76801 , H01L23/522 , H01L23/53228 , H01L24/03 , H01L24/05 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A method for fabricating a semiconductor device. The method includes providing a semiconductor substrate including a surface region. The method forms a first interlayer dielectric overlying the surface region and forms an interconnect layer overlying the first interlayer dielectric layer. The method also forms a low K dielectric layer overlying the interconnect layer, which has a predetermined shape. The method forms a copper interconnect layer overlying the low K dielectric layer. In a preferred embodiment, the low K dielectric layer maintains the predetermined shape using a dummy pattern structure provided within a portion of the low K dielectric layer to mechanically support and maintain the predetermined shape of the low K dielectric layer between the interconnect layer and the copper interconnect layer.
摘要翻译：一种半导体器件的制造方法。该方法包括提供包括表面区域的半导体衬底。该方法形成覆盖表面区域的第一层间电介质，并形成覆盖第一层间介质层的互连层。该方法还形成了覆盖互连层的低K电介质层，其具有预定的形状。该方法形成覆盖在低K电介质层上的铜互连层。在优选实施例中，低K电介质层使用设置在低K电介质层的一部分内的虚设图案结构来保持预定形状，以在互连层和铜之间机械地支撑和保持低K电介质层的预定形状互连层。

3. 发明授权

US07547595B2 Integration scheme method and structure for transistors using strained silicon 有权
标题翻译：使用应变硅的晶体管的集成方案和结构
公开(公告)号：US07547595B2
公开(公告)日：2009-06-16
申请号：US11471035
申请日：2006-06-19
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/7624 , H01L21/823807 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for forming CMOS integrated circuits. The method forms a blanket layer of silicon dioxide overlying an entirety of the surface region of a first well region and a second well region provided on a semiconductor substrate. The blanket layer of silicon dioxide is overlying the hard mask on the first gate structure and the second gate structure. The blanket layer of silicon dioxide is also overlying a region to be protected. Depending upon the embodiment, the region can be a sidewall spacer structure and portion of an MOS device on a peripheral region of the substrate. Of course, there can be other variations, modifications, and alternatives. The method protects the region to be protected using a masking layer, while the surface region of the first well region and the second well region being exposed. The method selectively removes exposed portions of the blanket layer of silicon dioxide, including the hard mask on the first gate structure and the second gate structure, while exposing a first polysilicon material on the first gate structure and while exposing a second polysilicon material on the second gate structure. The method strips the masking layer. The method also includes forming a silicided layer overlying the first polysilicon material on the first gate structure and the second polysilicon material on the second gate structure, while the region to be protected remains free from the silicided layer.
摘要翻译：一种用于形成CMOS集成电路的方法。该方法形成覆盖第一阱区的整个表面区域和设置在半导体衬底上的第二阱区的二氧化硅覆盖层。二氧化硅的覆盖层覆盖在第一栅极结构和第二栅极结构上的硬掩模上。二氧化硅的覆盖层也覆盖在要保护的区域上。根据实施例，该区域可以是衬底的外围区域上的侧壁间隔结构和MOS器件的部分。当然，可以有其他的变化，修改和替代。该方法利用掩模层保护被保护的区域，同时暴露第一阱区域和第二阱区域的表面区域。所述方法选择性地去除二氧化硅覆盖层的暴露部分，包括第一栅极结构和第二栅极结构上的硬掩模，同时暴露第一栅极结构上的第一多晶硅材料，同时在第二栅极结构上暴露第二多晶硅材料门结构。该方法剥离掩模层。该方法还包括在第一栅极结构上形成覆盖第一多晶硅材料的硅化物层和第二栅极结构上的第二多晶硅材料，同时待保护的区域保持不含硅化物层。

4. 发明授权

US07425488B2 Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors 有权
标题翻译：使用用于应变硅MOS晶体管的栅极图案化的纯二氧化硅硬掩模的方法和结构
公开(公告)号：US07425488B2
公开(公告)日：2008-09-16
申请号：US11245412
申请日：2005-10-05
申请人： Hanming Wu , Jiang Zhang , John Chen , Xian J Ning
发明人： Hanming Wu , Jiang Zhang , John Chen , Xian J Ning
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66545 , H01L29/66636
摘要： A partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material (e.g., silicon/germanium, silicon carbide) in an etched source region and an etched drain region. Preferably, the etched source region and the etched drain region are coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the fill material formed in the etched source region and the etched drain region.
摘要翻译：部分完成的半导体集成电路器件。该器件具有覆盖半导体衬底的半导体衬底和电介质层。该器件具有包括边缘的栅极结构和覆盖栅极结构的基本上纯的二氧化硅掩模结构。包括约400至约600埃基本上纯的二氧化硅掩模结构的厚度。器件具有在栅极结构的边缘上形成侧壁间隔物的电介质层，以保护包括边缘的栅极结构和覆盖栅极结构的纯二氧化硅掩模结构的暴露部分。该器件在蚀刻的源极区域和蚀刻的漏极区域中具有外延生长的填充材料（例如，硅/锗，碳化硅）。优选地，蚀刻的源极区域和蚀刻的漏极区域耦合到栅极结构。该装置在填充的源区和填充的漏极区之间具有至少从形成在蚀刻的源极区和蚀刻的漏极区中的填充材料的应变通道区。

5. 发明授权

US06794262B2 MIM capacitor structures and fabrication methods in dual-damascene structures 失效
公开(公告)号：US06794262B2
公开(公告)日：2004-09-21
申请号：US10252476
申请日：2002-09-23
申请人： Xian J. Ning , Keith Kwong Hon Wong
发明人： Xian J. Ning , Keith Kwong Hon Wong
IPC分类号： H01L2120
CPC分类号： H01L28/86 , H01L21/31604 , H01L21/76807 , H01L23/5223 , H01L28/55 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor (242/252) structure and method of forming the same. A dielectric layer (214) of a semiconductor device (200) is patterned with a dual damascene pattern having a first pattern (216) and a second pattern (218). The second pattern (218) has a greater depth than the first pattern (216). A conductive layer (226) is formed over the dielectric layer (214) in the first pattern, and a conductive layer is formed over the conductive layer in the first pattern (216). A dielectric layer (232), conductive layer (234), dielectric layer (236) and conductive layer (238) are disposed over the conductive layer (226) of the second pattern (218). Conductive layer (234), dielectric layer (232) and conductive layer (226) form a first MIM capacitor (252). Conductive layer (238), dielectric layer (236) and conductive layer (234) form a second MIM capacitor (242) parallel to the first MIM capacitor (242).

6. 发明授权

US06780775B2 Design of lithography alignment and overlay measurement marks on CMP finished damascene surface 有权
标题翻译： CMP成品镶嵌表面上的光刻对准和覆盖测量标记的设计
公开(公告)号：US06780775B2
公开(公告)日：2004-08-24
申请号：US09854760
申请日：2001-05-14
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L21302
CPC分类号： G03F9/708 , G03F9/7076 , G03F9/7084 , H01L21/822 , H01L23/544 , H01L27/222 , H01L2223/5442 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a semiconductor device having an alignment mark, the method comprising forming a first dielectric layer within which a trench having predetermined dimensions is etched and depositing a first layer of metal into the trench; forming a second dielectric layer over the first dielectric layer and over the first layer of metal; simultaneously etching lines and an opening into the second dielectric layer, at least one line used as a via extending to the first layer of metal; filling the lines and the opening, the filling controlled to fill the lines and to under fill the opening; performing chemical mechanical polishing of the plate; and depositing a non-transparent stack of layers onto the metal, whereby the non-transparent stack of layers conforms to the surface of the under filled opening resulting in an alignment mark on the non-transparent stack of layers in order to align successive layers.
摘要翻译：一种用于制造具有对准标记的半导体器件的方法，所述方法包括形成其中蚀刻具有预定尺寸的沟槽的第一介电层，并将第一金属层沉积到所述沟槽中; 在所述第一介电层上并在所述第一金属层上方形成第二电介质层; 同时蚀刻线和到第二介电层的开口，至少一条线用作延伸到第一金属层的通孔; 填充线和开口，填充控制填充线和填充开口; 进行板的化学机械抛光; 并且将不透明的层叠层沉积到金属上，由此不透明的层叠层与未填充的开口的表面一致，导致在非透明层叠层上的对准标记，以便对准连续的层。

7. 发明授权

US06451667B1 Self-aligned double-sided vertical MIMcap 有权
公开(公告)号：US06451667B1
公开(公告)日：2002-09-17
申请号：US09742918
申请日：2000-12-21
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L2120
CPC分类号： H01L28/82 , H01L28/90
摘要： A vertical MIM capacitor (140) including a first conductive line (124) and second conductive line (136) sandwiched around a vertical portion of a capacitor dielectric (134). Additional conductive lines (136) may be positioned vertically proximate first conductive lines (124) separated by another vertical portion of capacitor dielectric (134) to form a double-sided capacitor (142), increasing the capacitance. A plurality of vertical MIMcaps (140, 142) may be coupled together in parallel to increase the capacitance.

8. 发明授权

US06440753B1 Metal hard mask for ILD RIE processing of semiconductor memory devices to prevent oxidation of conductive lines 有权
标题翻译：金属硬掩模用于ILD RIE处理半导体存储器件以防止导电线的氧化
公开(公告)号：US06440753B1
公开(公告)日：2002-08-27
申请号：US09824596
申请日：2001-04-02
申请人： Xian J. Ning , Joachim Nuetzel
发明人： Xian J. Ning , Joachim Nuetzel
IPC分类号： H01L21467
CPC分类号： H01L21/0332 , B82Y10/00 , H01L27/222 , Y10S438/945
摘要： A method of patterning conductive lines (252) of a memory array integrated circuit (200) using a hard mask (244) and reactive ion etching (RIE). Using a hard mask (244) prevents oxidation of underlying conductive lines (210).
摘要翻译：使用硬掩模（244）和反应离子蚀刻（RIE）对存储阵列集成电路（200）的导线（252）进行图案化的方法。使用硬掩模（244）防止下面的导电线（210）的氧化。

9. 发明授权

US08158520B2 Method of forming a via structure dual damascene structure for the manufacture of semiconductor integrated circuit devices 有权
标题翻译：形成用于制造半导体集成电路器件的通孔结构双镶嵌结构的方法
公开(公告)号：US08158520B2
公开(公告)日：2012-04-17
申请号：US10969886
申请日：2004-10-20
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76807 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit device structure with a novel contact feature. The structure includes a substrate, a dielectric layer overlying the substrate, and a metal interconnect overlying the dielectric layer. A first interlayer dielectric layer is formed surrounding the metal interconnect. A second interlayer dielectric layer of a predetermined thickness is overlying the first interlayer dielectric layer. A trench opening of a first width is formed within an upper portion of the second interlayer dielectric layer. A first barrier layer is within and is overlying the trench opening of the first width. A contact opening of a second width is within a lower portion of the second interlayer dielectric layer. The second width is less than the first width. The lower portion of the second interlayer dielectric layer is coupled to the upper portion of the second interlayer dielectric layer within the predetermined thickness of the second interlayer dielectric. A second barrier layer is within and is overlying the opening of the contact opening and overlying the first barrier layer. A directional partially or completely removal of the second barrier forming a low contact resistance structure. A copper material is formed overlying the first barrier layer and the second barrier layer to substantially fill the contact opening and the trench within the second interlayer dielectric layer.
摘要翻译：具有新颖接触特征的集成电路器件结构。该结构包括衬底，覆盖衬底的电介质层和覆盖在电介质层上的金属互连。形成围绕金属互连的第一层间介质层。具有预定厚度的第二层间介质层覆盖在第一层间介电层上。在第二层间电介质层的上部形成有第一宽度的沟槽开口。第一阻挡层位于第一宽度的沟槽开口内并且覆盖第一宽度的沟槽开口。第二宽度的接触开口在第二层间电介质层的下部内。第二宽度小于第一宽度。第二层间电介质层的下部在第二层间电介质的预定厚度内耦合到第二层间电介质层的上部。第二阻挡层位于接触开口的开口内并且覆盖在第一阻挡层上方。定向部分地或完全地去除形成低接触电阻结构的第二阻挡层。形成覆盖在第一阻挡层和第二阻挡层上的铜材料，以基本上填充第二层间电介质层内的接触开口和沟槽。

10. 发明授权

US07479699B2 Seal ring structures with unlanded via stacks 有权
标题翻译：密封环结构，带有无底板的堆叠
公开(公告)号：US07479699B2
公开(公告)日：2009-01-20
申请号：US11611391
申请日：2006-12-15
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L23/48
CPC分类号： H01L23/585 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： Techniques for an integrated circuit device are provided. The integrated circuit device includes a semiconductor substrate, an integrated circuit, a dielectric layer, and a sealing structure. The sealing structure surrounds the integrated circuit and is disposed within the dielectric layer to prevent damage to the integrated circuit. The sealing structure includes a plurality of metal traces organized in vertical layers and a plurality of vias. Each via of the plurality of vias couples at least two metal traces of the plurality of metal traces from adjacent vertical layers. Each via of the plurality of vias contacts at least two orthogonal surfaces of a lower metal trace of the at least two metal traces. The plurality of metal traces and plurality of vias form a continuous boundary.
摘要翻译：提供了一种用于集成电路器件的技术。集成电路器件包括半导体衬底，集成电路，电介质层和密封结构。密封结构围绕集成电路并且设置在介电层内以防止对集成电路的损坏。密封结构包括以垂直层和多个通孔组织的多个金属迹线。多个通孔的每个通孔将多个金属迹线中的至少两个金属迹线与相邻的垂直层耦合。多个通孔的每个通孔接触至少两个金属迹线的下部金属迹线的至少两个正交表面。多个金属迹线和多个通孔形成连续的边界。

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