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1. 发明授权

US09917094B2 Semiconductor device having staggered pillars 有权
公开(公告)号：US09917094B2
公开(公告)日：2018-03-13
申请号：US14920223
申请日：2015-10-22
申请人： Wookhyoung Lee , Jongsik Chun , Sunil Shim , Jaeyoung Ahn , Juyul Lee , Kihyun Hwang , Hansoo Kim , Woonkyung Lee , Jaehoon Jang , Wonseok Cho
发明人： Wookhyoung Lee , Jongsik Chun , Sunil Shim , Jaeyoung Ahn , Juyul Lee , Kihyun Hwang , Hansoo Kim , Woonkyung Lee , Jaehoon Jang , Wonseok Cho
IPC分类号： G11C5/06 , H01L27/11565 , G11C7/00 , H01L23/48 , G11C7/18 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L27/02
CPC分类号： H01L27/11565 , G11C5/06 , G11C5/063 , G11C7/00 , G11C7/18 , H01L23/48 , H01L27/0207 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

2. 发明授权

US09177613B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09177613B2
公开(公告)日：2015-11-03
申请号：US14018885
申请日：2013-09-05
申请人： Wookhyoung Lee , Jongsik Chun , Sunil Shim , Jaeyoung Ahn , Juyul Lee , Kihyun Hwang , Hansoo Kim , Woonkyung Lee , Jaehoon Jang , Wonseok Cho
发明人： Wookhyoung Lee , Jongsik Chun , Sunil Shim , Jaeyoung Ahn , Juyul Lee , Kihyun Hwang , Hansoo Kim , Woonkyung Lee , Jaehoon Jang , Wonseok Cho
IPC分类号： G11C5/06 , G11C7/00 , H01L23/48 , G11C7/18 , H01L27/115 , H01L27/02
CPC分类号： H01L27/11565 , G11C5/06 , G11C5/063 , G11C7/00 , G11C7/18 , H01L23/48 , H01L27/0207 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.
摘要翻译：提供了一种半导体器件，其包括设置在基板上的栅极结构，插入在栅极结构之间的分离绝缘层以及通过每个栅极结构连接到基板的多个单元柱。每个栅极结构可以包括垂直堆叠在基板上的水平电极，并且相邻的单元柱之间的间隔是不均匀的。

3. 发明申请

US20100109065A1 THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES HAVING SUB-DIVIDED ACTIVE BARS AND METHODS OF MANUFACTURING SUCH DEVICES 有权
标题翻译：具有分包活性棒的三维非易失性存储器件及其制造方法
公开(公告)号：US20100109065A1
公开(公告)日：2010-05-06
申请号：US12612125
申请日：2009-11-04
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L27/115
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

4. 发明授权

US08426301B2 Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices 有权
标题翻译：具有分割活动杆的三维非易失性存储器件及其制造方法
公开(公告)号：US08426301B2
公开(公告)日：2013-04-23
申请号：US13197026
申请日：2011-08-03
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L21/4763
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

5. 发明申请

US20110287623A1 Three-Dimensional Nonvolatile Memory Devices Having Sub-Divided Active Bars and Methods of Manufacturing Such Devices 有权
标题翻译：具有子分割活动条的三维非易失性存储器件及其制造方法
公开(公告)号：US20110287623A1
公开(公告)日：2011-11-24
申请号：US13197026
申请日：2011-08-03
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L21/336
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

6. 发明授权

US08013389B2 Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices 有权
标题翻译：具有分割活动杆的三维非易失性存储器件及其制造方法
公开(公告)号：US08013389B2
公开(公告)日：2011-09-06
申请号：US12612125
申请日：2009-11-04
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L29/66
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

7. 发明申请

US20130313629A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20130313629A1
公开(公告)日：2013-11-28
申请号：US13830208
申请日：2013-03-14
申请人： Sunil Shim , Jaehoon Jang , Hansoo Kim , Sungmi Hwang , Wonseok Cho , Jinsoo Lim
发明人： Sunil Shim , Jaehoon Jang , Hansoo Kim , Sungmi Hwang , Wonseok Cho , Jinsoo Lim
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L27/11556 , H01L27/11582
摘要： A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer, and forming a conductive pattern.
摘要翻译：一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过第一多层结构形成第一孔，在第一孔中形成第一半导体图案在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器层，形成导电图案。

8. 发明申请

US20110065270A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20110065270A1
公开(公告)日：2011-03-17
申请号：US12858057
申请日：2010-08-17
申请人： Sunil Shim , Jaehoon Jang , Hansoo Kim , Sungmi Hwang , Wonseok Cho , Jinsoo Lim
发明人： Sunil Shim , Jaehoon Jang , Hansoo Kim , Sungmi Hwang , Wonseok Cho , Jinsoo Lim
IPC分类号： H01L21/8229
CPC分类号： H01L29/7926 , H01L27/11556 , H01L27/11582
摘要： A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer along surfaces of the plurality of recess regions, and forming a conductive pattern within each recess region.
摘要翻译：一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过所述第一多层结构形成第一孔，在所述第一孔中形成第一半导体图案在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器层，并且形成导电体每个凹陷区域内的图案。

9. 发明申请

US20100315875A1 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME 有权
标题翻译：具有垂直结构的非易失性存储器件及其操作方法
公开(公告)号：US20100315875A1
公开(公告)日：2010-12-16
申请号：US12860049
申请日：2010-08-20
申请人： Doogon Kim , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jaehun Jeong
发明人： Doogon Kim , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jaehun Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L29/66825 , H01L29/7881
摘要： Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.
摘要翻译：提供了一种操作非易失性存储器件的方法。该方法包括对第一NAND串的第一和第二串选择晶体管中的每一个施加导通电压，将第一和第二电压分别施加到第二NAND串的第三和第四串选择晶体管，并将高电压施加到与第一和第二NAND串的存储单元相连的字线。

10. 发明授权

US08488381B2 Non-volatile memory device having vertical structure and method of operating the same 有权
标题翻译：具有垂直结构的非易失性存储器件及其操作方法
公开(公告)号：US08488381B2
公开(公告)日：2013-07-16
申请号：US12860049
申请日：2010-08-20
申请人： Doogon Kim , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jaehun Jeong
发明人： Doogon Kim , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jaehun Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L29/66825 , H01L29/7881
摘要： Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.
摘要翻译：提供了一种操作非易失性存储器件的方法。该方法包括对第一NAND串的第一和第二串选择晶体管中的每一个施加导通电压，将第一和第二电压分别施加到第二NAND串的第三和第四串选择晶体管，并将高电压施加到与第一和第二NAND串的存储单元相连的字线。

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