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1. 发明授权

US08461656B2 Device structures for in-plane and out-of-plane sensing micro-electro-mechanical systems (MEMS) 有权
标题翻译：用于平面内和平面外感测微机电系统（MEMS）的器件结构
公开(公告)号：US08461656B2
公开(公告)日：2013-06-11
申请号：US12827848
申请日：2010-06-30
申请人： Woo Tae Park , Lisa H. Karlin , Lianjun Liu , Heinz Loreck , Hemant D. Desai
发明人： Woo Tae Park , Lisa H. Karlin , Lianjun Liu , Heinz Loreck , Hemant D. Desai
IPC分类号： H04R23/00
CPC分类号： B81C1/00182 , B81B2201/0235 , B81C2203/0792 , G01P15/0802 , G01P15/125 , H01L29/84
摘要： A device structure is made using a first conductive layer over a first wafer. An isolated conductive region is formed in the first conductive layer surrounded by a first opening in the conductive layer. A second wafer has a first insulating layer and a conductive substrate, wherein the conductive substrate has a first major surface adjacent to the first insulating layer. The insulating layer is attached to the isolated conductive region. The conductive substrate is thinned to form a second conductive layer. A second opening is formed through the second conductive layer and the first insulating layer to the isolated conductive region. The second opening is filled with a conductive plug wherein the conductive plug contacts the isolated conductive region. The second conductive region is etched to form a movable finger over the isolated conductive region. A portion of the insulating layer under the movable finger is removed.
摘要翻译：使用第一晶片上的第一导电层制造器件结构。在由导电层中的第一开口包围的第一导电层中形成隔离的导电区域。第二晶片具有第一绝缘层和导电衬底，其中导电衬底具有与第一绝缘层相邻的第一主表面。绝缘层附接到隔离导电区域。导电基板被薄化以形成第二导电层。通过第二导电层和第一绝缘层形成第二开口到隔离的导电区域。第二开口填充有导电插头，其中导电插头接触隔离的导电区域。蚀刻第二导电区域以在隔离的导电区域上形成可移动的手指。去除可动指状物下面的绝缘层的一部分。

2. 发明申请

US20120001277A1 METHODS FOR MAKING IN-PLANE AND OUT-OF-PLANE SENSING MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) 有权
标题翻译：用于制造平面和平面外感测微电子机械系统（MEMS）的方法
公开(公告)号：US20120001277A1
公开(公告)日：2012-01-05
申请号：US12827848
申请日：2010-06-30
申请人： Woo Tae Park , Lisa H. Karlin , Lianjun Liu , Heinz Loreck , Hemant D. Desai
发明人： Woo Tae Park , Lisa H. Karlin , Lianjun Liu , Heinz Loreck , Hemant D. Desai
IPC分类号： H01L29/84 , H01L21/28
CPC分类号： B81C1/00182 , B81B2201/0235 , B81C2203/0792 , G01P15/0802 , G01P15/125 , H01L29/84
摘要： A device structure is made using a first conductive layer over a first wafer. An isolated conductive region is formed in the first conductive layer surrounded by a first opening in the conductive layer. A second wafer has a first insulating layer and a conductive substrate, wherein the conductive substrate has a first major surface adjacent to the first insulating layer. The insulating layer is attached to the isolated conductive region. The conductive substrate is thinned to form a second conductive layer. A second opening is formed through the second conductive layer and the first insulating layer to the isolated conductive region. The second opening is filled with a conductive plug wherein the conductive plug contacts the isolated conductive region. The second conductive region is etched to form a movable finger over the isolated conductive region. A portion of the insulating layer under the movable finger is removed.
摘要翻译：使用第一晶片上的第一导电层制造器件结构。在由导电层中的第一开口包围的第一导电层中形成隔离的导电区域。第二晶片具有第一绝缘层和导电衬底，其中导电衬底具有与第一绝缘层相邻的第一主表面。绝缘层附接到隔离导电区域。导电基板被薄化以形成第二导电层。通过第二导电层和第一绝缘层形成第二开口到隔离的导电区域。第二开口填充有导电插头，其中导电插头接触隔离的导电区域。蚀刻第二导电区域以在隔离的导电区域上形成可移动的手指。去除可动指状物下面的绝缘层的一部分。

3. 发明授权

US08119431B2 Method of forming a micro-electromechanical system (MEMS) having a gap stop 有权
标题翻译：形成具有间隙停止的微机电系统（MEMS）的方法
公开(公告)号：US08119431B2
公开(公告)日：2012-02-21
申请号：US12632940
申请日：2009-12-08
申请人： Woo Tae Park , Lisa H. Karlin , Lianjun Liu
发明人： Woo Tae Park , Lisa H. Karlin , Lianjun Liu
IPC分类号： H01L21/00
CPC分类号： H01L23/10 , B81B2203/0118 , B81C3/001 , B81C2203/0118 , B81C2203/035 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a micro-electromechanical system (MEMS) includes providing a cap substrate, providing a support substrate, depositing a conductive material over the support substrate, patterning the conductive material to form a gap stop and a contact, wherein the gap stop is separated form the contact by an opening, forming a bonding material over the contact and in the opening, wherein the gap stop and the contact prevent the bonding material from extending outside the opening, and attaching the cap substrate to the support substrate by the step of forming the bonding material. In addition, the structure is described.
摘要翻译：一种形成微机电系统（MEMS）的方法包括提供盖基板，提供支撑基板，在支撑基板上沉积导电材料，图案化导电材料以形成间隙止挡件和接触件，其中间隙止挡件通过开口分离形成接触，在接触和开口中形成接合材料，其中间隙停止和接触防止接合材料延伸到开口外部，并且通过步骤将盖基板附接到支撑基板形成接合材料。另外，对该结构进行说明。

4. 发明申请

US20110133294A1 MICRO ELECTROMECHANICAL SYSTEMS (MEMS) HAVING A GAP STOP AND METHOD THEREFOR 有权
标题翻译：微机电系统（MEMS）及其方法
公开(公告)号：US20110133294A1
公开(公告)日：2011-06-09
申请号：US12632940
申请日：2009-12-08
申请人： Woo Tae Park , Lisa H. Karlin , Lianjun Liu
发明人： Woo Tae Park , Lisa H. Karlin , Lianjun Liu
IPC分类号： H01L29/84 , H01L21/50
CPC分类号： H01L23/10 , B81B2203/0118 , B81C3/001 , B81C2203/0118 , B81C2203/035 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a micro-electromechanical system (MEMS) includes providing a cap substrate, providing a support substrate, depositing a conductive material over the support substrate, patterning the conductive material to form a gap stop and a contact, wherein the gap stop is separated form the contact by an opening, forming a bonding material over the contact and in the opening, wherein the gap stop and the contact prevent the bonding material from extending outside the opening, and attaching the cap substrate to the support substrate by the step of forming the bonding material. In addition, the structure is described.
摘要翻译：一种形成微机电系统（MEMS）的方法包括提供盖基板，提供支撑基板，在支撑基板上沉积导电材料，图案化导电材料以形成间隙止挡件和接触件，其中间隙止挡件通过开口分离形成接触，在接触和开口中形成接合材料，其中间隙停止和接触防止接合材料延伸到开口外部，并且通过步骤将盖基板附接到支撑基板形成接合材料。另外，对该结构进行说明。

5. 发明授权

US08921203B2 Method of forming an integrated circuit having varying substrate depth 有权
标题翻译：形成具有变化的衬底深度的集成电路的方法
公开(公告)号：US08921203B2
公开(公告)日：2014-12-30
申请号：US13750419
申请日：2013-01-25
申请人： Lisa H. Karlin , Hemant D. Desai , Kemiao Jia
发明人： Lisa H. Karlin , Hemant D. Desai , Kemiao Jia
IPC分类号： H01L21/30
CPC分类号： B81B7/0077 , B81B3/0021 , B81B2201/0235 , B81B2203/0163 , G01P15/0802 , G01P15/18 , G01P2015/086 , H01L29/66007 , H01L29/84
摘要： A method for forming a semiconductor device includes providing a substrate having a first major surface and a second major surface, removing a first portion of the substrate to form a cavity at the first major surface of the substrate, bonding the first major surface of the substrate to a carrier substrate after forming the cavity, and reducing a thickness of the substrate. The method further includes forming a first accelerometer device at the second major surface such that at least a portion of the first accelerometer device is over the cavity and forming a second accelerometer device at the second major surface such that the second accelerometer device is not disposed over the cavity.
摘要翻译：一种形成半导体器件的方法包括提供具有第一主表面和第二主表面的衬底，去除衬底的第一部分以在衬底的第一主表面处形成空腔，将衬底的第一主表面在形成空腔之后到载体基板，并且减小基板的厚度。该方法还包括在第二主表面处形成第一加速度计装置，使得第一加速度计装置的至少一部分在空腔之上并且在第二主表面处形成第二加速度计装置，使得第二加速度计装置不被布置在空腔。

6. 发明申请

US20110042761A1 EUTECTIC FLOW CONTAINMENT IN A SEMICONDUCTOR FABRICATION PROCESS 有权
标题翻译：半导体制造工艺中的保护性流动容纳
公开(公告)号：US20110042761A1
公开(公告)日：2011-02-24
申请号：US12914859
申请日：2010-10-28
申请人： Lisa H. Karlin , Hemant D. Desai
发明人： Lisa H. Karlin , Hemant D. Desai
IPC分类号： H01L23/00 , H01L29/84
CPC分类号： H01L23/10 , B81C1/00269 , B81C2203/019 , H01L23/04 , H01L2924/0002 , H01L2924/01079 , H01L2924/00
摘要： A disclosed semiconductor fabrication process includes forming a first bonding structure on a first surface of a cap wafer, forming a second bonding structure on a first surface of a device wafer, and forming a device structure on the device wafer. One or more eutectic flow containment structures are formed on the cap wafer, the device wafer, or both. The flow containment structures may include flow containment micro-cavities (FCMCs) and flow containment micro-levee (FCMLs). The FCMLs may be elongated ridges overlying the first surface of the device wafer and extending substantially parallel to the bonding structure. The FCMLs may include interior FCMLs lying within a perimeter of the bonding structure, exterior FCMLs lying outside of the bonding structure perimeter, or both. When the two wafers are bonded, the FCMLs and FCMCs confine flow of the eutectic material to the region of the bonding structure.
摘要翻译：所公开的半导体制造工艺包括在盖晶片的第一表面上形成第一接合结构，在器件晶片的第一表面上形成第二接合结构，并在器件晶片上形成器件结构。在盖晶片，器件晶片或两者上形成一个或多个共晶流阻塞结构。流动容纳结构可以包括流动容纳微空腔（FCMC）和流动容纳微堤（FCML）。 FCML可以是覆盖在器件晶片的第一表面上并且基本上平行于接合结构延伸的细长脊。 FCML可以包括位于结合结构的周边内部的内部FCML，位于结合结构周边外部的外部FCML或两者。当两个晶片结合时，FCML和FCMC将共晶材料的流动限制在接合结构的区域。

7. 发明授权

US08652865B2 Attaching a MEMS to a bonding wafer 有权
标题翻译：将MEMS连接到接合晶片
公开(公告)号：US08652865B2
公开(公告)日：2014-02-18
申请号：US13210563
申请日：2011-08-16
申请人： Lisa H. Karlin , Hemant D. Desai
发明人： Lisa H. Karlin , Hemant D. Desai
IPC分类号： H01L21/00
CPC分类号： B81C1/00269
摘要： A MEMS is attached to a bonding wafer in part by forming a support layer over the MEMS. A first eutectic layer is formed over the support layer. The eutectic layer is patterned into segments to relieve stress. A second eutectic layer is formed over the bonding wafer. A eutectic bond is formed with the segments and the second eutectic layer to attach the bonding wafer to the MEMS.
摘要翻译：通过在MEMS上形成支撑层，部分地将MEMS连接到接合晶片。第一共晶层形成在支撑层上。共晶层被图案化成段以减轻应力。在接合晶片上形成第二共晶层。与段和第二共晶层形成共晶键，以将接合晶片附接到MEMS。

8. 发明授权

US07846815B2 Eutectic flow containment in a semiconductor fabrication process 有权
标题翻译：半导体制造工艺中的共晶流动遏制
公开(公告)号：US07846815B2
公开(公告)日：2010-12-07
申请号：US12414324
申请日：2009-03-30
申请人： Lisa H. Karlin , Hemant D. Desai
发明人： Lisa H. Karlin , Hemant D. Desai
IPC分类号： H01L23/00
CPC分类号： H01L23/10 , B81C1/00269 , B81C2203/019 , H01L23/04 , H01L2924/0002 , H01L2924/01079 , H01L2924/00
摘要： A disclosed semiconductor fabrication process includes forming a first bonding structure on a first surface of a cap wafer, forming a second bonding structure on a first surface of a device wafer, and forming a device structure on the device wafer. One or more eutectic flow containment structures are formed on the cap wafer, the device wafer, or both. The flow containment structures may include flow containment micro-cavities (FCMCs) and flow containment micro-levee (FCMLs). The FCMLs may be elongated ridges overlying the first surface of the device wafer and extending substantially parallel to the bonding structure. The FCMLs may include interior FCMLs lying within a perimeter of the bonding structure, exterior FCMLs lying outside of the bonding structure perimeter, or both. When the two wafers are bonded, the FCMLs and FCMCs confine flow of the eutectic material to the region of the bonding structure.
摘要翻译：所公开的半导体制造工艺包括在盖晶片的第一表面上形成第一接合结构，在器件晶片的第一表面上形成第二接合结构，并在器件晶片上形成器件结构。在盖晶片，器件晶片或两者上形成一个或多个共晶流阻塞结构。流动容纳结构可以包括流动容纳微空腔（FCMC）和流动容纳微堤（FCML）。 FCML可以是覆盖在器件晶片的第一表面上并且基本上平行于接合结构延伸的细长脊。 FCML可以包括位于结合结构的周边内部的内部FCML，位于结合结构周边外部的外部FCML或两者。当两个晶片结合时，FCML和FCMC将共晶材料的流动限制在接合结构的区域。

9. 发明申请

US20150084138A1 INTEGRATED CIRCUIT HAVING VARYING SUBSTRATE DEPTH AND METHOD OF FORMING SAME 有权
标题翻译：具有变化的基底深度的集成电路及其形成方法
公开(公告)号：US20150084138A1
公开(公告)日：2015-03-26
申请号：US14561726
申请日：2014-12-05
申请人： Lisa H. Karlin , Hemant D. Desai , Kemiao Jia
发明人： Lisa H. Karlin , Hemant D. Desai , Kemiao Jia
IPC分类号： B81B7/00 , B81B3/00
CPC分类号： B81B7/0077 , B81B3/0021 , B81B2201/0235 , B81B2203/0163 , G01P15/0802 , G01P15/18 , G01P2015/086 , H01L29/66007 , H01L29/84
摘要： A semiconductor device is formed such that a semiconductor substrate of the device has a non-uniform thickness. A cavity is etched at a selected side of the semiconductor substrate, and the selected side is then fusion bonded to another substrate, such as a carrier substrate. After fusion bonding, the side of the semiconductor substrate opposite the selected side is ground to a defined thickness. Accordingly, the semiconductor substrate has a uniform thickness except in the area of the cavity, where the substrate is thinner. Devices that benefit from a thinner substrate, such as an accelerometer, can be formed over the cavity.
摘要翻译：半导体器件形成为使得器件的半导体衬底具有不均匀的厚度。在半导体衬底的选定侧蚀刻空腔，然后将所选择的侧面熔合到另一衬底，例如载体衬底。在熔接后，将半导体衬底与选定侧相对的侧面被研磨成规定的厚度。因此，半导体衬底除了空腔的区域之外具有均匀的厚度，其中衬底较薄。可以在空腔上形成从更薄的衬底（例如加速度计）受益的器件。

10. 发明申请

US20140225206A1 PRESSURE LEVEL ADJUSTMENT IN A CAVITY OF A SEMICONDUCTOR DIE 审中-公开
标题翻译：在半导体芯片的压力水平调整
公开(公告)号：US20140225206A1
公开(公告)日：2014-08-14
申请号：US13764246
申请日：2013-02-11
申请人： Yizhen Lin , Chad S. Dawson , Hemant D. Desai , Lisa H. Karlin , Keith L. Kraver , Mark E. Schlarmann
发明人： Yizhen Lin , Chad S. Dawson , Hemant D. Desai , Lisa H. Karlin , Keith L. Kraver , Mark E. Schlarmann
IPC分类号： B81B7/00 , B81B3/00
CPC分类号： B81B7/0038 , B81B7/02 , B81C2203/0109
摘要： A semiconductor die (20) includes a substrate (30) and microelectronic devices (22, 26) located at a surface (32) of the substrate (30). A cap (34) is coupled to the substrate (30), and the microelectronic device (22) is positioned in the cavity (24). An outgassing material structure (36) is located within a cavity (24) between the cap (34) and the substrate (30). The outgassing material structure (36) releases trapped gas (37) to increase the pressure within the cavity (24) from an initial pressure level (96) to a second pressure level (94). The cap (34) may include another cavity (28) containing another microelectronic device (26). A getter material (42) may be located within the cavity (28). The getter material (42) is activated to absorb residual gas (46) in the cavity (28) and decrease the pressure within the cavity (28) from the initial pressure level (96) to a third pressure level (92).
摘要翻译：半导体管芯（20）包括位于衬底（30）的表面（32）处的衬底（30）和微电子器件（22,26）。盖（34）耦合到基板（30），并且微电子器件（22）定位在空腔（24）中。排气材料结构（36）位于盖（34）和基板（30）之间的空腔（24）内。排气材料结构（36）释放截留的气体（37）以将空腔（24）内的压力从初始压力水平（96）增加到第二压力水平（94）。盖（34）可以包括另一个包含另一微电子装置（26）的空腔（28）。吸气材料（42）可以位于空腔（28）内。吸气剂材料（42）被激活以吸收空腔（28）中的残余气体（46）并将空腔（28）内的压力从初始压力水平（96）降低到第三压力水平（92）。

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