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1. 发明授权

US07250335B2 Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin 有权
标题翻译：制造集成电路器件的方法包括具有增加的对准余量的自对准触点
公开(公告)号：US07250335B2
公开(公告)日：2007-07-31
申请号：US11201803
申请日：2005-08-11
申请人： Won-suk Yang , Ki-nam Kim
发明人： Won-suk Yang , Ki-nam Kim
IPC分类号： H01L21/8239
CPC分类号： H01L21/76897
摘要： An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions. A plurality of bit line structures are on the substrate, extending transverse to the word line structures and contacting the second conductive pads. Related methods of fabrication are also described.
摘要翻译：诸如存储器件的集成电路器件包括衬底以及衬底中的多行有源区域，有源区域以交错图案排列，使得第一行的有源区域与隔离的部分对准分隔相邻第二行的有效区域的区域。源极和漏极区域处于有源区域中并且被布置成使得每个有源区域包括设置在两个源极区域之间的漏极区域。多个字线结构位于衬底上，横向于有源区的行布置，使得字线结构跨越源极区域和漏极区域之间的有源区域。导电焊盘的各行布置在相应的相邻字线结构之间，包括源极区上的第一导电焊盘，漏极区上的第二导电焊盘以及分离有源区的隔离区上的第三导电。多个位线结构在基板上，横向于字线结构延伸并与第二导电焊盘接触。还描述了相关的制造方法。

2. 发明授权

US07164204B2 Integrated circuit devices with an auxiliary pad for contact hole alignment 失效
标题翻译：具有用于接触孔对准的辅助焊盘的集成电路器件
公开(公告)号：US07164204B2
公开(公告)日：2007-01-16
申请号：US10770738
申请日：2004-02-03
申请人： Won-suk Yang , Ki-nam Kim
发明人： Won-suk Yang , Ki-nam Kim
IPC分类号： H01L23/52
CPC分类号： H01L24/02 , H01L2924/01004 , H01L2924/01033 , H01L2924/14 , H01L2924/30105
摘要： An integrated circuit device structure which avoids misalignment when a contact hole is formed to expose a contact pad and a method of fabricating the same, are provided. The integrated circuit device includes a semiconductor substrate having a conductive region and an insulating region, a contact pad on the conductive region of the semiconductor substrate, an auxiliary pad adjacent to the contact pad, and an interlevel insulating layer on the semiconductor substrate and having a contact hole for exposing both the contact pad and the auxiliary pad.
摘要翻译：提供了当形成接触孔以露出接触焊盘时避免未对准的集成电路器件结构及其制造方法。集成电路器件包括具有导电区域和绝缘区域的半导体衬底，半导体衬底的导电区域上的接触焊盘，与接触焊盘相邻的辅助焊盘以及半导体衬底上的层间绝缘层，并具有用于露出接触垫和辅助垫的接触孔。

3. 发明申请

US20050272251A1 Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin 有权
标题翻译：制造集成电路器件的方法包括具有增加的对准余量的自对准触点
公开(公告)号：US20050272251A1
公开(公告)日：2005-12-08
申请号：US11201803
申请日：2005-08-11
申请人： Won-suk Yang , Ki-nam Kim
发明人： Won-suk Yang , Ki-nam Kim
IPC分类号： H01L21/768 , H01L21/60 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L21/336 , H01L21/4763
CPC分类号： H01L21/76897
摘要： An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions. A plurality of bit line structures are on the substrate, extending transverse to the word line structures and contacting the second conductive pads. Related methods of fabrication are also described.
摘要翻译：诸如存储器件的集成电路器件包括衬底以及衬底中的多行有源区域，有源区域以交错图案排列，使得第一行的有源区域与隔离的部分对准分隔相邻第二行的有效区域的区域。源极和漏极区域处于有源区域中并且被布置成使得每个有源区域包括设置在两个源极区域之间的漏极区域。多个字线结构位于衬底上，横向于有源区的行布置，使得字线结构跨越源极区域和漏极区域之间的有源区域。导电焊盘的相应行设置在相应的相邻字线结构之间，包括源区上的第一导电焊盘，漏极区上的第二导电焊盘以及分离有源区的隔离区上的第三导电。多个位线结构在基板上，横向于字线结构延伸并与第二导电焊盘接触。还描述了相关的制造方法。

4. 发明申请

US20050070094A1 Semiconductor device having multilayer interconnection structure and manufacturing method thereof 有权
标题翻译：具有多层互连结构的半导体器件及其制造方法
公开(公告)号：US20050070094A1
公开(公告)日：2005-03-31
申请号：US10989930
申请日：2004-11-16
申请人： Won-suk Yang , Ki-nam Kim , Hong-sik Jeong
发明人： Won-suk Yang , Ki-nam Kim , Hong-sik Jeong
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L23/522 , H01L27/108 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/76801 , H01L21/76804 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a width of an entrance portion adjacent to the surface of the ILD layer larger than the width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a width larger than that of the second contact stud. The second contact stud has a width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad. The entrance portion of the first contact stud has a width about 30-60% larger than that of the contacting portion.
摘要翻译：半导体器件及其制造方法包括半导体衬底，形成在半导体衬底上的层间电介质层（ILD）层，形成在ILD层中的第一接触柱，具有与ILD层的表面相邻的入口部分的宽度大于邻近半导体衬底的接触部分的宽度;以及第二接触柱，其与第一接触螺柱间隔开并形成在ILD层中。半导体器件还包括形成在ILD层上的接合焊盘，其接触第二接触柱的表面，其宽度大于第二接触柱的宽度。第二接触柱具有与入口部相同的接触部的宽度。此外，在着陆焊盘的侧壁上形成至少一个包括蚀刻阻挡材料的间隔物，并且在着陆焊盘上形成蚀刻停止层。第一接触柱的入口部分的宽度比接触部分的宽度大30-60％。

5. 发明授权

US07300888B2 Methods of manufacturing integrated circuit devices having an encapsulated insulation layer 失效
标题翻译：具有封装绝缘层的集成电路器件的制造方法
公开(公告)号：US07300888B2
公开(公告)日：2007-11-27
申请号：US10008700
申请日：2001-12-07
申请人： Hong-sik Jeong , Soo-ho Shin , Won-suk Yang , Ki-nam Kim
发明人： Hong-sik Jeong , Soo-ho Shin , Won-suk Yang , Ki-nam Kim
IPC分类号： H01L21/31 , H01L21/469 , H01L21/3205 , H01L21/4763 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/316 , H01L21/76895 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device is manufactured by forming an insulating layer on a substrate. A capping layer is formed on the insulating layer and both the capping layer and the insulating layer are patterned. Insulating spacers are formed on sidewalls of the insulating layer so that the insulating spacers, the capping layer, and the substrate enclose the insulating layer.
摘要翻译：通过在基板上形成绝缘层来制造集成电路器件。在绝缘层上形成覆盖层，并对覆盖层和绝缘层进行图案化。绝缘垫片形成在绝缘层的侧壁上，使得绝缘隔离物，覆盖层和衬底包围绝缘层。

6. 发明授权

US06953959B2 Integrated circuit devices including self-aligned contacts with increased alignment margin 有权
标题翻译：集成电路器件包括具有增加的对准裕度的自对准触点
公开(公告)号：US06953959B2
公开(公告)日：2005-10-11
申请号：US10156477
申请日：2002-05-28
申请人： Won-suk Yang , Ki-nam Kim
发明人： Won-suk Yang , Ki-nam Kim
IPC分类号： H01L21/768 , H01L21/60 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/00
CPC分类号： H01L21/76897
摘要： An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions. A plurality of bit line structures are on the substrate, extending transverse to the word line structures and contacting the second conductive pads. Related methods of fabrication are also described.
摘要翻译：诸如存储器件的集成电路器件包括衬底以及衬底中的多行有源区域，有源区域以交错图案排列，使得第一行的有源区域与隔离的部分对准分隔相邻第二行的有效区域的区域。源极和漏极区域处于有源区域中并且被布置成使得每个有源区域包括设置在两个源极区域之间的漏极区域。多个字线结构位于衬底上，横向于有源区的行布置，使得字线结构跨越源极区域和漏极区域之间的有源区域。导电焊盘的相应行设置在相应的相邻字线结构之间，包括源区上的第一导电焊盘，漏极区上的第二导电焊盘以及分离有源区的隔离区上的第三导电。多个位线结构在基板上，横向于字线结构延伸并与第二导电焊盘接触。还描述了相关的制造方法。

7. 发明授权

US06836019B2 Semiconductor device having multilayer interconnection structure and manufacturing method thereof 有权
标题翻译：具有多层互连结构的半导体器件及其制造方法
公开(公告)号：US06836019B2
公开(公告)日：2004-12-28
申请号：US09999104
申请日：2001-10-31
申请人： Won-suk Yang , Ki-nam Kim , Hong-sik Jeong
发明人： Won-suk Yang , Ki-nam Kim , Hong-sik Jeong
IPC分类号： H01L2348
CPC分类号： H01L23/485 , H01L21/76801 , H01L21/76804 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a line width of an entrance portion adjacent to the surface of the ILD layer larger than the line width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a line width larger than that of the second contact stud. The second contact stud has a line width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad. The entrance portion of the first contact stud has a line width about 30-60% larger than that of the contacting portion.
摘要翻译：半导体器件及其制造方法包括半导体衬底，在半导体衬底上形成的层间电介质层（ILD）层，形成在ILD层中的第一接触柱，具有与ILD的表面相邻的入口部的线宽度大于与半导体衬底相邻的接触部分的线宽度的第二接触柱，以及形成在ILD层中的与第一接触柱隔开的第二接触柱。半导体器件还包括形成在ILD层上的接合焊盘，其接触第二接触柱的表面，其线宽大于第二接触柱的线宽。第二接触螺柱具有与入口部分相同的接触部分的线宽度。此外，在着陆焊盘的侧壁上形成至少一个包括蚀刻阻挡材料的间隔物，并且在着陆焊盘上形成蚀刻停止层。第一接触柱的入口部分具有比接触部分的线宽大30-60％的线宽。

8. 发明授权

US07510963B2 Semiconductor device having multilayer interconnection structure and manufacturing method thereof 有权
标题翻译：具有多层互连结构的半导体器件及其制造方法
公开(公告)号：US07510963B2
公开(公告)日：2009-03-31
申请号：US10989930
申请日：2004-11-16
申请人： Won-suk Yang , Ki-nam Kim , Hong-sik Jeong
发明人： Won-suk Yang , Ki-nam Kim , Hong-sik Jeong
IPC分类号： H01L21/4763
CPC分类号： H01L23/485 , H01L21/76801 , H01L21/76804 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a width of an entrance portion adjacent to the surface of the ILD layer larger than the width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a width larger than that of the second contact stud. The second contact stud has a width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad. The entrance portion of the first contact stud has a width about 30-60% larger than that of the contacting portion.
摘要翻译：半导体器件及其制造方法包括半导体衬底，形成在半导体衬底上的层间电介质层（ILD）层，形成在ILD层中的第一接触柱，具有与ILD层的表面相邻的入口部分的宽度大于邻近半导体衬底的接触部分的宽度;以及第二接触柱，其与第一接触螺柱间隔开并形成在ILD层中。半导体器件还包括形成在ILD层上的接合焊盘，其接触第二接触柱的表面，其宽度大于第二接触柱的宽度。第二接触柱具有与入口部相同的接触部的宽度。此外，在着陆焊盘的侧壁上形成至少一个包括蚀刻阻挡材料的间隔物，并且在着陆焊盘上形成蚀刻停止层。第一接触柱的入口部分的宽度比接触部分的宽度大30-60％。

9. 发明授权

US06699762B2 Methods of fabricating integrated circuit devices with contact hole alignment 失效
标题翻译：制造具有接触孔对准的集成电路器件的方法
公开(公告)号：US06699762B2
公开(公告)日：2004-03-02
申请号：US10171247
申请日：2002-06-12
申请人： Won-suk Yang , Ki-nam Kim
发明人： Won-suk Yang , Ki-nam Kim
IPC分类号： H01L21441
CPC分类号： H01L24/02 , H01L2924/01004 , H01L2924/01033 , H01L2924/14 , H01L2924/30105
摘要： An integrated circuit device structure which avoids misalignment when a contact hole is formed to expose a contact pad and a method of fabricating the same, are provided. The integrated circuit device includes a semiconductor substrate having a conductive region and an insulating region, a contact pad on the conductive region of the semiconductor substrate, an auxiliary pad adjacent to the contact pad, and an interlevel insulating layer on the semiconductor substrate and having a contact hole for exposing both the contact pad and the auxiliary pad.
摘要翻译：提供了当形成接触孔以露出接触焊盘时避免未对准的集成电路器件结构及其制造方法。集成电路器件包括具有导电区域和绝缘区域的半导体衬底，半导体衬底的导电区域上的接触焊盘，与接触焊盘相邻的辅助焊盘以及半导体衬底上的层间绝缘层，并具有用于露出接触垫和辅助垫的接触孔。

10. 发明授权

US06822335B2 Method for arranging wiring line including power reinforcing line and semiconductor device having power reinforcing line 有权
标题翻译：用于布置包括电力加强线的布线和具有电力加强线的半导体器件的方法
公开(公告)号：US06822335B2
公开(公告)日：2004-11-23
申请号：US10452096
申请日：2003-05-30
申请人： Won-suk Yang , Jae-young Lee , Chang-hyun Cho , Ki-nam Kim
发明人： Won-suk Yang , Jae-young Lee , Chang-hyun Cho , Ki-nam Kim
IPC分类号： H01L2131
CPC分类号： G11C7/06 , G11C5/14 , G11C11/4091
摘要： A method for arranging a power supply line in a semiconductor device including a plurality of memory cell array blocks and a semiconductor device are provided in order to supply stable operating voltages, such as a power supply voltage and a ground voltage, to a sense amplifier allocated to each of the plurality of memory cell array blocks. The method includes the steps of arranging a plurality of first interconnections that extend in one direction and are spaced apart from one another on a semiconductor substrate on which the plurality of memory cell array blocks are formed, forming a first insulating layer on the plurality of first interconnections, arranging a plurality of power reinforcing lines that extends in one direction and are spaced apart from one another on the plurality of first interconnections on the first insulating layer, forming a second insulating layer on the plurality of power reinforcing lines, and arranging a plurality of second interconnections that intersect the plurality of first interconnections and the plurality of power reinforcing lines on the second insulating layer. The plurality of second interconnections include a first group and a second group, and the second interconnections in the second group are electrically connected to the plurality of power reinforcing lines on the plurality of memory cell array blocks via contact plugs formed in the second insulating layer.
摘要翻译：提供了一种用于在包括多个存储单元阵列块和半导体器件的半导体器件中布置电源线的方法，以便向分配的读出放大器提供诸如电源电压和接地电压的稳定工作电压到多个存储单元阵列块中的每一个。该方法包括以下步骤：在形成有多个存储单元阵列块的半导体衬底上布置在一个方向上延伸并且彼此间隔开的多个第一互连，在多个第一绝缘层上形成第一绝缘层布置多个在一个方向上延伸并且在第一绝缘层上的多个第一互连上彼此间隔开的功率增强线，在多个功率增强线上形成第二绝缘层，并且布置多个的第二互连，其与第二绝缘层上的多个第一互连和多个功率增强线相交。多个第二互连包括第一组和第二组，并且第二组中的第二互连通过形成在第二绝缘层中的接触插塞电连接到多个存储单元阵列块上的多个功率增强线。

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