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1. 发明授权

US07833890B2 Semiconductor device having a pair of fins and method of manufacturing the same 失效
标题翻译：具有一对翅片的半导体器件及其制造方法
公开(公告)号：US07833890B2
公开(公告)日：2010-11-16
申请号：US12457366
申请日：2009-06-09
申请人： Won-joo Kim , June-mo Koo , Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Jong-jin Lee
发明人： Won-joo Kim , June-mo Koo , Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Jong-jin Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.
摘要翻译：示例性实施例涉及半导体器件及其制造方法。根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。栅绝缘层可以插入在栅电极和一对鳍之间。

2. 发明申请

US20090253255A1 Semiconductor device having a pair of fins and method of manufacturing the same 失效
标题翻译：具有一对翅片的半导体器件及其制造方法
公开(公告)号：US20090253255A1
公开(公告)日：2009-10-08
申请号：US12457366
申请日：2009-06-09
申请人： Won-joo Kim , June-mo Koo , Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Jong-jin Lee
发明人： Won-joo Kim , June-mo Koo , Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Jong-jin Lee
IPC分类号： H01L21/28
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.
摘要翻译：示例性实施例涉及半导体器件及其制造方法。根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。栅绝缘层可以插入在栅电极和一对鳍之间。

3. 发明授权

US07551491B2 Unit cell of a non-volatile memory device, a non-volatile memory device and method thereof 有权
标题翻译：非易失性存储器件的单元，非易失性存储器件及其方法
公开(公告)号：US07551491B2
公开(公告)日：2009-06-23
申请号：US11715404
申请日：2007-03-08
申请人： Won-joo Kim , Suk-pil Kim , Jae-woong Hyun , Yoon-dong Park , June-mo Koo
发明人： Won-joo Kim , Suk-pil Kim , Jae-woong Hyun , Yoon-dong Park , June-mo Koo
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C16/0491 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Unit cells of a non-volatile memory device and a method thereof are provided. In an example, the unit cell may include a first memory transistor and a second memory transistor connected to each other in series and further connected in common to a word line, the first and second memory transistors including first and second storage nodes, respectively, the first and second storage nodes configured to execute concurrent memory operations. In another example, the unit cell may include a semiconductor substrate in which first and second bit line regions are defined, first and second storage node layers respectively formed on the semiconductor substrate between the first and second bit line regions, a first pass gate electrode formed on the semiconductor substrate between the first bit line region and the first storage node layer, a second pass gate electrode formed on the semiconductor substrate between the second bit line region and the second storage node layer, a third pass gate electrode formed on the semiconductor substrate between the first and second storage node layers, a third bit line region formed in a portion of the semiconductor substrate under the third pass gate electrode and a control gate electrode extending across the first and second storage node layers. The example unit cells may be implemented within a non-volatile memory device (e.g., a flash memory device), such that the non-volatile memory device may include a plurality of example unit cells.
摘要翻译：提供非易失性存储器件的单元电池及其方法。在一个示例中，单元可以包括串联连接并进一步连接到字线的第一存储晶体管和第二存储晶体管，第一和第二存储晶体管分别包括第一和第二存储节点，配置为执行并发存储器操作的第一和第二存储节点。在另一示例中，单元可以包括其中限定了第一和第二位线区域的半导体衬底，分别形成在第一和第二位线区域之间的半导体衬底上的第一和第二存储节点层，形成的第一遍栅极电极在第一位线区域和第一存储节点层之间的半导体衬底上，形成在第二位线区域和第二存储节点层之间的半导体衬底上的第二遍栅极电极，形成在半导体衬底上的第三栅极电极在所述第一和第二存储节点层之间形成第三位线区域，所述第三位线区域形成在所述第三栅极电极下方的所述半导体衬底的一部分中，以及跨越所述第一和第二存储节点层延伸的控制栅电极。示例性单元单元可以在非易失性存储器件（例如，闪存器件）内实现，使得非易失性存储器件可以包括多个示例单位单元。

4. 发明申请

US20080111199A1 Semiconductor device having a pair of fins and method of manufacturing the same 失效
标题翻译：具有一对翅片的半导体器件及其制造方法
公开(公告)号：US20080111199A1
公开(公告)日：2008-05-15
申请号：US11976004
申请日：2007-10-19
申请人： Suk-pil KIM , Yoon-dong Park , Jong-Jin Lee , Won-joo Kim , June-mo Koo , Seung-hwan Song
发明人： Suk-pil KIM , Yoon-dong Park , Jong-Jin Lee , Won-joo Kim , June-mo Koo , Seung-hwan Song
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.
摘要翻译：示例性实施例涉及半导体器件及其制造方法。根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。栅绝缘层可以插入在栅电极和一对鳍之间。

5. 发明授权

US07932551B2 Nonvolatile memory device and method of fabricating the same comprising a dual fin structure 失效
标题翻译：非易失性存储器件及其制造方法包括双鳍结构
公开(公告)号：US07932551B2
公开(公告)日：2011-04-26
申请号：US11902511
申请日：2007-09-21
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/42336 , H01L29/66803
摘要： A nonvolatile memory device is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type includes first and second fins. A common bit line electrode connects one end of the first fin to one end of the second fin. Control gate electrodes cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode positioned between the common bit line electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode positioned between the first string selection gate electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins.
摘要翻译：提供非易失性存储器件。在非易失性存储器件中，第一导电类型的半导体衬底包括第一和第二鳍片。公共位线电极将第一鳍片的一端连接到第二鳍片的一端。控制栅电极覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。位于公共位线电极和控制栅电极之间的第一串选择栅电极可以覆盖第一和第二散热片并且横跨第一和第二散热片的每一个的顶表面膨胀。位于第一串选择栅极电极和控制栅电极之间的第二串选择栅电极可以覆盖第一和第二散热片并且横跨第一和第二散热片的每一个的顶表面膨胀。

6. 发明授权

US07894265B2 Non-volatile memory device and operation method of the same 有权
标题翻译：非易失性存储器件及其操作方法相同
公开(公告)号：US07894265B2
公开(公告)日：2011-02-22
申请号：US12081679
申请日：2008-04-18
申请人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
发明人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
IPC分类号： G11C5/06 , G11C16/04 , G11C16/10 , G11C16/26
CPC分类号： G11C16/0483 , H01L27/11521 , H01L27/11568
摘要： The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor. A method of programming a target cell of the memory device includes activating selection transistors connected to a main string and substring of the target cell.
摘要翻译：非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。编程存储器件的目标单元的方法包括激活连接到目标单元的主串和子串的选择晶体管。

7. 发明授权

US07829932B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07829932B2
公开(公告)日：2010-11-09
申请号：US11980632
申请日：2007-10-31
申请人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-woong Hyun , Sung-jae Byun
发明人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-woong Hyun , Sung-jae Byun
IPC分类号： H01L29/788
CPC分类号： H01L29/785 , H01L21/76897 , H01L29/41791 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7851 , H01L29/7881 , H01L29/792 , H01L2029/7858
摘要： Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.
摘要翻译：示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。半导体器件包括半导体衬底，半导体柱和接触插塞。半导体衬底包括至少一对使用（或功能）作为活性区的翅片。半导体柱可以插入翅片的部分之间以连接散热片。接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

8. 发明授权

US07750393B2 Non-volatile memory device with independent channel regions adjacent different sides of a common control gate 失效
标题翻译：具有与公共控制门不同侧相邻的独立通道区域的非易失性存储器件
公开(公告)号：US07750393B2
公开(公告)日：2010-07-06
申请号：US11987008
申请日：2007-11-26
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/7885 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42344 , H01L29/42352 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： Provided are example embodiments of a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a control gate electrode arranged on a semiconductor substrate, a gate insulating layer interposed between the semiconductor substrate and the control gate electrode, a storage node layer interposed between the gate insulating layer and the control gate electrode, a blocking insulating layer interposed between the storage node layer and the control gate electrode, first dopant doping regions along a first side of the control gate electrode, and second dopant doping regions along a second side of the control gate electrode. The first dopant doping regions may alternate with the second dopant doping regions. Stated differently, each of the second dopant doping regions may be arranged in a region on the second side of the control gate electrode that is adjacent to one of the first dopant doping regions.
摘要翻译：提供了非易失性存储器件的示例性实施例及其制造方法。非易失性存储器件可以包括布置在半导体衬底上的控制栅电极，介于半导体衬底和控制栅电极之间的栅极绝缘层，介于栅极绝缘层和控制栅电极之间的存储节点层，插入在所述存储节点层和所述控制栅电极之间的阻挡绝缘层，沿着所述控制栅电极的第一侧的第一掺杂剂掺杂区域和沿着所述控制栅电极的第二侧的第二掺杂剂掺杂区域。第一掺杂剂掺杂区域可以与第二掺杂剂掺杂区域交替。换句话说，每个第二掺杂剂掺杂区域可以被布置在与第一掺杂剂掺杂区域中的一个相邻的控制栅电极的第二侧上的区域中。

9. 发明申请

US20090122613A1 Non-volatile memory device and method of operating the same 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20090122613A1
公开(公告)日：2009-05-14
申请号：US12149213
申请日：2008-04-29
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon , Tae-hee Lee
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C16/10 , G11C2213/71
摘要： A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.
摘要翻译：非易失性存储器件可以包括多个堆叠半导体层，多个NAND串，公共位线，公共源极线和/或多个串选择线。多个NAND串可以在多个半导体层上。多个NAND串中的每一个可以包括布置在NAND单元阵列中的多个存储单元和/或至少一个串选择晶体管。公共位线可以在存储器单元的第一端处共同连接到每个NAND串。公共源极线可以在存储器单元的第二端处共同连接到每个NAND串。多个串选择线可以耦合到包括在每个NAND串中的至少一个串选择晶体管，使得施加到公共位线的信号被选择性地施加到NAND串。

10. 发明申请

US20080025106A1 Unit cell of a non-volatile memory device, a non-volatile memory device and method thereof 有权
标题翻译：非易失性存储器件的单元，非易失性存储器件及其方法
公开(公告)号：US20080025106A1
公开(公告)日：2008-01-31
申请号：US11715404
申请日：2007-03-08
申请人： Won-joo Kim , Suk-pil Kim , Jae-woong Hyun , Yoon-dong Park , June-mo Koo
发明人： Won-joo Kim , Suk-pil Kim , Jae-woong Hyun , Yoon-dong Park , June-mo Koo
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C16/0491 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Unit cells of a non-volatile memory device and a method thereof are provided. In an example, the unit cell may include a first memory transistor and a second memory transistor connected to each other in series and further connected in common to a word line, the first and second memory transistors including first and second storage nodes, respectively, the first and second storage nodes configured to execute concurrent memory operations. In another example, the unit cell may include a semiconductor substrate in which first and second bit line regions are defined. first and second storage node layers respectively formed on the semiconductor substrate between the first and second bit line regions, a first pass gate electrode formed on the semiconductor substrate between the first bit line region and the first storage node layer, a second pass gate electrode formed on the semiconductor substrate between the second bit line region and the second storage node layer, a third pass gate electrode formed on the semiconductor substrate between the first and second storage node layers, a third bit line region formed in a portion of the semiconductor substrate under the third pass gate electrode and a control gate electrode extending across the first and second storage node layers. The example unit cells may be implemented within a non-volatile memory device (e.g., a flash memory device), such that the non-volatile memory device may include a plurality of example unit cells.
摘要翻译：提供非易失性存储器件的单元电池及其方法。在一个示例中，单元可以包括串联连接并进一步连接到字线的第一存储晶体管和第二存储晶体管，第一和第二存储晶体管分别包括第一和第二存储节点，配置为执行并发存储器操作的第一和第二存储节点。在另一示例中，单元可以包括其中限定了第一和第二位线区域的半导体衬底。分别形成在第一和第二位线区域之间的半导体衬底上的第一和第二存储节点层，形成在第一位线区域和第一存储节点层之间的半导体衬底上的第一遍栅极电极，形成的第二遍栅极电极在第二位线区域和第二存储节点层之间的半导体衬底上，形成在第一和第二存储节点层之间的半导体衬底上的第三遍栅极电极，形成在半导体衬底的一部分中的第三位线区域所述第三通道栅极电极和跨越所述第一和第二存储节点层延伸的控制栅极电极。示例性单元单元可以在非易失性存储器件（例如，闪存器件）内实现，使得非易失性存储器件可以包括多个示例单位单元。

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