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1. 发明申请

US20080157182A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080157182A1
公开(公告)日：2008-07-03
申请号：US11980632
申请日：2007-10-31
申请人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-Woong Hyun , Sung-jae Byun
发明人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-Woong Hyun , Sung-jae Byun
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/785 , H01L21/76897 , H01L29/41791 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7851 , H01L29/7881 , H01L29/792 , H01L2029/7858
摘要： Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.
摘要翻译：示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。半导体器件包括半导体衬底，半导体柱和接触插塞。半导体衬底包括至少一对使用（或功能）作为活性区的翅片。半导体柱可以插入翅片的部分之间以连接散热片。接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

2. 发明授权

US07829932B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07829932B2
公开(公告)日：2010-11-09
申请号：US11980632
申请日：2007-10-31
申请人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-woong Hyun , Sung-jae Byun
发明人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-woong Hyun , Sung-jae Byun
IPC分类号： H01L29/788
CPC分类号： H01L29/785 , H01L21/76897 , H01L29/41791 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7851 , H01L29/7881 , H01L29/792 , H01L2029/7858
摘要： Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.
摘要翻译：示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。半导体器件包括半导体衬底，半导体柱和接触插塞。半导体衬底包括至少一对使用（或功能）作为活性区的翅片。半导体柱可以插入翅片的部分之间以连接散热片。接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

3. 发明申请

US20080157176A1 Nonvolatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080157176A1
公开(公告)日：2008-07-03
申请号：US11902511
申请日：2007-09-21
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/42336 , H01L29/66803
摘要： A nonvolatile memory device having lower bit line contact resistance and a method of fabricating the same is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type may include first and second fins. A common bit line electrode may connect one end of the first fin to one end of the second fin. A plurality of control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode may be positioned between the common bit line electrode and the plurality of control gate electrodes. The first string selection gate electrode may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode may be positioned between the first string selection gate electrode and the plurality of control gate electrodes. The second string selection gate electrode may cover the first and second fins and expand across the top surface of each of the first and second fins. The first fin under the first string selection gate electrode and the second fin under the second string selection gate electrode may have a second conductivity type opposite to the first conductivity type.
摘要翻译：提供一种具有较低位线接触电阻的非易失性存储器件及其制造方法。在非易失性存储器件中，第一导电类型的半导体衬底可以包括第一和第二鳍片。公共位线电极可将第一鳍片的一端连接到第二鳍片的一端。多个控制栅极电极可以覆盖第一和第二鳍片并且跨越第一和第二鳍片中的每一个的顶表面膨胀。第一串选择栅极可以位于公共位线电极和多个控制栅电极之间。第一串选择栅电极可以覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。第二串选择栅电极可以位于第一串选择栅电极和多个控制栅电极之间。第二串选择栅电极可以覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。第一串选择栅电极下的第一鳍和第二串选择栅电极下的第二鳍可以具有与第一导电类型相反的第二导电类型。

4. 发明授权

US07932551B2 Nonvolatile memory device and method of fabricating the same comprising a dual fin structure 失效
标题翻译：非易失性存储器件及其制造方法包括双鳍结构
公开(公告)号：US07932551B2
公开(公告)日：2011-04-26
申请号：US11902511
申请日：2007-09-21
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/42336 , H01L29/66803
摘要： A nonvolatile memory device is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type includes first and second fins. A common bit line electrode connects one end of the first fin to one end of the second fin. Control gate electrodes cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode positioned between the common bit line electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode positioned between the first string selection gate electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins.
摘要翻译：提供非易失性存储器件。在非易失性存储器件中，第一导电类型的半导体衬底包括第一和第二鳍片。公共位线电极将第一鳍片的一端连接到第二鳍片的一端。控制栅电极覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。位于公共位线电极和控制栅电极之间的第一串选择栅电极可以覆盖第一和第二散热片并且横跨第一和第二散热片的每一个的顶表面膨胀。位于第一串选择栅极电极和控制栅电极之间的第二串选择栅电极可以覆盖第一和第二散热片并且横跨第一和第二散热片的每一个的顶表面膨胀。

5. 发明申请

US20070019479A1 Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions 有权
标题翻译：具有对应于一对通道区域的单个栅电极的半导体器件和随机存取存储器
公开(公告)号：US20070019479A1
公开(公告)日：2007-01-25
申请号：US11393750
申请日：2006-03-31
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
IPC分类号： G11C7/10
CPC分类号： H01L29/66795 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/11507 , H01L27/2436 , H01L29/785
摘要： A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.
摘要翻译：半导体器件可以包括半导体衬底上的至少一对散热片。可以在每个鳍中形成沟道区。半导体器件还可以包括对应于每对沟道区的栅电极，同时电连接到形成在相应散热片上的至少一个源中的每一个的源极接触插塞以及电连接到至少一个漏斗同时形成在相应的翅片上。

6. 发明授权

US07352037B2 Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions 有权
标题翻译：具有对应于一对通道区域的单个栅电极的半导体器件和随机存取存储器
公开(公告)号：US07352037B2
公开(公告)日：2008-04-01
申请号：US11393750
申请日：2006-03-31
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
IPC分类号： H01L29/94
CPC分类号： H01L29/66795 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/11507 , H01L27/2436 , H01L29/785
摘要： A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.
摘要翻译：半导体器件可以包括半导体衬底上的至少一对散热片。可以在每个鳍中形成沟道区。半导体器件还可以包括对应于每对沟道区的栅电极，同时电连接到形成在相应散热片上的至少一个源中的每一个的源极接触插塞以及电连接到至少一个漏斗同时形成在相应的翅片上。

7. 发明授权

US07649784B2 Memory cell programming methods capable of reducing coupling effects 失效
标题翻译：能够减少耦合效应的存储单元编程方法
公开(公告)号：US07649784B2
公开(公告)日：2010-01-19
申请号：US12000493
申请日：2007-12-13
申请人： Kyoung-Iae Cho , Jae-woong Hyun , Sung-jae Byun , Kyu-charn Park , Yoon-dong Park , Choong-ho Lee
发明人： Kyoung-Iae Cho , Jae-woong Hyun , Sung-jae Byun , Kyu-charn Park , Yoon-dong Park , Choong-ho Lee
IPC分类号： G11C11/03
CPC分类号： G11C16/0483 , G11C11/5628 , G11C2211/5648
摘要： In a memory cell programming method, first through n-th programming operations are performed to program first through n-th bits of the n bits of data using the plurality of threshold voltage distributions. The first through n-th programming operations are performed sequentially. A threshold voltage difference between threshold voltage distributions used in the n-th programming operation is less than or equal to at least one threshold voltage difference between threshold voltage distributions used in the first through (n−1)-th programming operations.
摘要翻译：在存储单元编程方法中，执行第一至第n编程操作，以使用多个阈值电压分布对n位数据的第一至第n位进行编程。顺序执行第一至第n编程操作。在第n编程操作中使用的阈值电压分布之间的阈值电压差小于或等于在第一至第（n-1）编程操作中使用的阈值电压分布之间的至少一个阈值电压差。

8. 发明授权

US07911842B2 Memory cell programming method and semiconductor device for simultaneously programming a plurality of memory block groups 有权
标题翻译：用于同时编程多个存储块组的存储单元编程方法和半导体器件
公开(公告)号：US07911842B2
公开(公告)日：2011-03-22
申请号：US12081568
申请日：2008-04-17
申请人： Ju-hee Park , Jae-woong Hyun , Yoon-dong Park , Kyoung-lae Cho , Sung-jae Byun , Seung-hwan Song , Jun-jin Kong , Sung-chung Park
发明人： Ju-hee Park , Jae-woong Hyun , Yoon-dong Park , Kyoung-lae Cho , Sung-jae Byun , Seung-hwan Song , Jun-jin Kong , Sung-chung Park
IPC分类号： G11C16/04
CPC分类号： H01L29/7883 , G11C16/10
摘要： Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an ith bit of the data may be simultaneously written to two or more memory block groups from among the plurality memory block groups, and then an i+1th bit of the data may be simultaneously written to the two or more memory block groups from among the plurality memory block groups, where i is a natural number less than M.
摘要翻译：提供了一种存储器单元编程方法和半导体器件，其可以能够同时将数据位和数据的另一位写入多个存储块。其中将M位数据写入多个存储块的存储器编程方法可以包括数据分割操作和数据写入操作，其中M可以是自然数。在数据划分操作中，多个存储块可以被划分为多个存储块组。在数据写入操作中，数据的第i位可以从多个存储器块组中同时写入两个或更多个存储块组，然后数据的第i + 1位可以被同时写入两个或更多个多个存储块组中的存储块组，其中i是小于M的自然数。

9. 发明授权

US07729175B2 Method of writing/reading data into/from memory cell and page buffer using different codes for writing and reading operations 有权
标题翻译：使用不同的代码进行写入和读取操作，从存储单元和页面缓冲区写入/读取数据的方法
公开(公告)号：US07729175B2
公开(公告)日：2010-06-01
申请号：US12010481
申请日：2008-01-25
申请人： Kyoung-lae Cho , Yoon-dong Park , Jun-jin Kong , Seung-hoon Lee , Jae-woong Hyun , Sung-jae Byun , Ju-hee Park , Seung-hwan Song
发明人： Kyoung-lae Cho , Yoon-dong Park , Jun-jin Kong , Seung-hoon Lee , Jae-woong Hyun , Sung-jae Byun , Ju-hee Park , Seung-hwan Song
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C2211/5642
摘要： Provided are a method of writing/reading data into/from a memory cell and a page buffer using different codes for the writing and reading operations. The method of writing/reading data into/from a memory cell that has a plurality of threshold voltage distributions includes a data writing operation and a data reading operation. In the data writing operation, data having a plurality of bits is written into the memory cell by using a plurality of writing codes corresponding to threshold voltage distributions. In the data reading operation, the data having a plurality of bits is read from the memory cell by using reading codes corresponding to the threshold voltage distributions from among the threshold voltage distributions. In the method of writing/reading data into/from a memory cell, a part of the writing codes is different from a corresponding part of the reading codes.
摘要翻译：提供了一种将数据写入/从存储单元读取数据的方法和使用不同代码进行写入和读取操作的页面缓冲器。对具有多个阈值电压分布的存储单元写入/读取数据的方法包括数据写入操作和数据读取操作。在数据写入操作中，通过使用与阈值电压分布对应的多个写入代码，将具有多个位的数据写入存储单元。在数据读取操作中，通过使用与阈值电压分布中的阈值电压分布相对应的读取代码，从存储单元读取具有多个位的数据。在将数据写入/从存储单元读取的方法中，写入代码的一部分与读取代码的相应部分不同。

10. 发明申请

US20080285352A1 Method of writing/reading data into/from memory cell and page buffer using different codes for writing and reading operations 有权
标题翻译：使用不同的代码进行写入和读取操作，从存储单元和页面缓冲区写入/读取数据的方法
公开(公告)号：US20080285352A1
公开(公告)日：2008-11-20
申请号：US12010481
申请日：2008-01-25
申请人： Kyoung-lae Cho , Yoon-dong Park , Jun-jin Kong , Seung-hoon Lee , Jae-woong Hyun , Sung-jae Byun , Ju-hee Park , Seung-hwan Song
发明人： Kyoung-lae Cho , Yoon-dong Park , Jun-jin Kong , Seung-hoon Lee , Jae-woong Hyun , Sung-jae Byun , Ju-hee Park , Seung-hwan Song
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C2211/5642
摘要： Provided are a method of writing/reading data into/from a memory cell and a page buffer using different codes for the writing and reading operations. The method of writing/reading data into/from a memory cell that has a plurality of threshold voltage distributions includes a data writing operation and a data reading operation. In the data writing operation, data having a plurality of bits is written into the memory cell by using a plurality of writing codes corresponding to threshold voltage distributions. In the data reading operation, the data having a plurality of bits is read from the memory cell by using reading codes corresponding to the threshold voltage distributions from among the threshold voltage distributions. In the method of writing/reading data into/from a memory cell, a part of the writing codes is different from a corresponding part of the reading codes.
摘要翻译：提供了一种将数据写入/从存储单元读取数据的方法和使用不同代码进行写入和读取操作的页面缓冲器。对具有多个阈值电压分布的存储单元写入/读取数据的方法包括数据写入操作和数据读取操作。在数据写入操作中，通过使用与阈值电压分布对应的多个写入代码，将具有多个位的数据写入存储单元。在数据读取操作中，通过使用与阈值电压分布中的阈值电压分布相对应的读取代码，从存储单元读取具有多个位的数据。在将数据写入/从存储单元读取的方法中，写入代码的一部分与读取代码的相应部分不同。

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