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1. 发明授权

US08541841B2 Semiconductor devices and semiconductor device manufacturing methods 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US08541841B2
公开(公告)日：2013-09-24
申请号：US13412248
申请日：2012-03-05
申请人： Won-joo Kim , Sang-moo Choi , Tae-hee Lee , Yoon-dong Park
发明人： Won-joo Kim , Sang-moo Choi , Tae-hee Lee , Yoon-dong Park
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/76224 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/1207 , H01L29/7841
摘要： Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure.
摘要翻译：半导体器件和半导体器件制造方法。半导体器件制造方法可以通过使用选择性蚀刻在体半导体衬底的一个或多个局部区域中形成具有绝缘体上硅（SOI）结构的存储单元。因此，与具有SOI结构的存储单元相比，可以向外围设备施加不同的偏置电压。

2. 发明申请

US20120161277A1 SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE MANUFACTURING METHODS 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20120161277A1
公开(公告)日：2012-06-28
申请号：US13412248
申请日：2012-03-05
申请人： Won-joo KIM , Sang-moo Choi , Tae-hee Lee , Yoon-dong Park
发明人： Won-joo KIM , Sang-moo Choi , Tae-hee Lee , Yoon-dong Park
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/76224 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/1207 , H01L29/7841
摘要： Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure.
摘要翻译：半导体器件和半导体器件制造方法。半导体器件制造方法可以通过使用选择性蚀刻在体半导体衬底的一个或多个局部区域中形成具有绝缘体上硅（SOI）结构的存储单元。因此，与具有SOI结构的存储单元相比，可以向外围设备施加不同的偏置电压。

3. 发明申请

US20100133647A1 Semiconductor devices and semiconductor device manufacturing methods 审中-公开
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20100133647A1
公开(公告)日：2010-06-03
申请号：US12591718
申请日：2009-11-30
申请人： Won-joo Kim , Sang-moo Choi , Tae-hee Lee , Yoon-dong Park
发明人： Won-joo Kim , Sang-moo Choi , Tae-hee Lee , Yoon-dong Park
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L27/1203 , H01L21/76224 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/1207 , H01L29/7841
摘要： Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure.
摘要翻译：半导体器件和半导体器件制造方法。半导体器件制造方法可以通过使用选择性蚀刻在体半导体衬底的一个或多个局部区域中形成具有绝缘体上硅（SOI）结构的存储单元。因此，与具有SOI结构的存储单元相比，可以向外围设备施加不同的偏置电压。

4. 发明申请

US20100177566A1 Non-volatile memory device having stacked structure, and memory card and electronic system including the same 有权
标题翻译：具有堆叠结构的非易失性存储器件，以及包括该堆叠结构的存储卡和电子系统
公开(公告)号：US20100177566A1
公开(公告)日：2010-07-15
申请号：US12656043
申请日：2010-01-14
申请人： Won-joo Kim , Yoon-dong Park , Jung-hun Sung , Yong-koo Kyoung , Sang-moo Choi , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , Jung-hun Sung , Yong-koo Kyoung , Sang-moo Choi , Tae-hee Lee
IPC分类号： G11C16/04
CPC分类号： H01L27/11578 , G11C16/0483 , G11C16/08 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11556
摘要： Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set.
摘要翻译：提供了具有堆叠结构的非易失性存储器件，以及存储卡和包括其的系统。非易失性存储器件可以包括衬底。堆叠的NAND单元阵列可以具有至少一个NAND组，并且每个NAND组可以包括垂直堆叠在衬底上的多个NAND串。至少一个信号线可以布置在衬底上，以便与至少一个NAND组共同耦合。

5. 发明授权

US08385122B2 Non-volatile memory device having stacked structure, and memory card and electronic system including the same 有权
标题翻译：具有堆叠结构的非易失性存储器件，以及包括其的存储卡和电子系统
公开(公告)号：US08385122B2
公开(公告)日：2013-02-26
申请号：US12656043
申请日：2010-01-14
申请人： Won-joo Kim , Yoon-dong Park , Jung-hun Sung , Yong-koo Kyoung , Sang-moo Choi , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , Jung-hun Sung , Yong-koo Kyoung , Sang-moo Choi , Tae-hee Lee
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L27/11578 , G11C16/0483 , G11C16/08 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11556
摘要： Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set.
摘要翻译：提供了具有堆叠结构的非易失性存储器件，以及存储卡和包括其的系统。非易失性存储器件可以包括衬底。堆叠的NAND单元阵列可以具有至少一个NAND组，并且每个NAND组可以包括垂直堆叠在衬底上的多个NAND串。至少一个信号线可以布置在衬底上，以便与至少一个NAND组共同耦合。

6. 发明申请

US20100133600A1 Semiconductor devices having increased sensing margin 审中-公开
标题翻译：具有增加的感测裕度的半导体器件
公开(公告)号：US20100133600A1
公开(公告)日：2010-06-03
申请号：US12591686
申请日：2009-11-30
申请人： Won-joo Kim , Sang-moo Choi , Tae-hee Lee , Yoon-dong Park , Dae-kil Cha
发明人： Won-joo Kim , Sang-moo Choi , Tae-hee Lee , Yoon-dong Park , Dae-kil Cha
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L29/7881 , G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： One transistor (1-T) dynamic random access memories (DRAM) having improved sensing margins that are relatively independent of the amount of carriers stored in a body region thereof.
摘要翻译：具有改善的感测余量的一个晶体管（1-T）动态随机存取存储器（DRAM），其相对独立于存储在其身体区域中的载体的量。

7. 发明申请

US20100038719A1 Semiconductor apparatuses and methods of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100038719A1
公开(公告)日：2010-02-18
申请号：US12461131
申请日：2009-07-31
申请人： Won-Joo Kim , Tae-hee Lee , Yoon-dong Park , Sang-moo Choi , Dae-kll Cha
发明人： Won-Joo Kim , Tae-hee Lee , Yoon-dong Park , Sang-moo Choi , Dae-kll Cha
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/0688 , H01L27/108 , H01L27/10882
摘要： Disclosed are semiconductor apparatuses and methods of fabricating the same. According to the methods, the number of operations for fabricating the semiconductor apparatuses having a plurality of layers may be the same as the number of operations for fabricating a semiconductor apparatus having one layer. The semiconductor apparatuses may include first active regions extending in the same direction, in parallel, separated from each other and including first and second impurity doped regions on opposite ends of the first active regions from each other. The semiconductor apparatuses may further include second active regions on a layer above the first active regions, extending in the same direction as the first active regions, separated from each other, in parallel, and including first and second impurity doped regions on opposite ends of the second active regions from each other.
摘要翻译：公开半导体装置及其制造方法。根据该方法，用于制造具有多个层的半导体装置的操作次数可以与制造具有一层的半导体装置的操作次数相同。半导体装置可以包括在相同方向上并联延伸的第一有源区，彼此分离，并且包括彼此在第一有源区的相对端上的第一和第二杂质掺杂区。半导体装置还可以包括在第一有源区上方的层上的与第一有源区相同方向的第二有源区，该第一有源区平行彼此分开，并且包括第一和第二杂质掺杂区，第二活跃区域。

8. 发明申请

US20090016107A1 Methods of operating nonvolatile memory devices 有权
标题翻译：操作非易失性存储设备的方法
公开(公告)号：US20090016107A1
公开(公告)日：2009-01-15
申请号：US12073314
申请日：2008-03-04
申请人： Won-joo Kim , Tae-hee Lee , Jae-woong Hyun , Yoon-dong Park
发明人： Won-joo Kim , Tae-hee Lee , Jae-woong Hyun , Yoon-dong Park
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/34
摘要： Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell.
摘要翻译：提供了非易失性存储器件的操作方法。在操作包括多个存储单元的非易失性存储器件的方法中，通过在其中记录有记录数据的存储单元的通道上感应升压电压来稳定记录数据。从多个存储单元中选择存储单元，并且所选存储单元的通道上的升压电压由连接到所选存储单元的至少一个存储单元的通道电压引起。

9. 发明申请

US20080315285A1 Non-volatile memory devices and methods of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080315285A1
公开(公告)日：2008-12-25
申请号：US12071452
申请日：2008-02-21
申请人： Tae-hee Lee , Jae-woong Hyun , Ju-hee Park , In-kyeong Yoo , Yoon-dong Park , Won-joo Kim , Jung-hoon Lee
发明人： Tae-hee Lee , Jae-woong Hyun , Ju-hee Park , In-kyeong Yoo , Yoon-dong Park , Won-joo Kim , Jung-hoon Lee
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42336
摘要： Non-volatile memory devices and methods of fabricating the same are provided. The non-volatile memory devices may include a semiconductor substrate having a pair of sidewall channel regions extending from the semiconductor substrate and opposite to each other, and a floating gate electrode between the pair of sidewall channel regions and protruding from the semiconductor substrate. A control gate electrode may be formed on the semiconductor substrate and a portion of the floating gate electrode.
摘要翻译：提供非易失性存储器件及其制造方法。非易失性存储器件可以包括具有从半导体衬底延伸并且彼此相对的一对侧壁沟道区的半导体衬底，以及在该对侧壁沟道区之间并从半导体衬底突出的浮置栅电极。控制栅电极可以形成在半导体衬底和浮栅电极的一部分上。

10. 发明授权

US07894265B2 Non-volatile memory device and operation method of the same 有权
标题翻译：非易失性存储器件及其操作方法相同
公开(公告)号：US07894265B2
公开(公告)日：2011-02-22
申请号：US12081679
申请日：2008-04-18
申请人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
发明人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
IPC分类号： G11C5/06 , G11C16/04 , G11C16/10 , G11C16/26
CPC分类号： G11C16/0483 , H01L27/11521 , H01L27/11568
摘要： The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor. A method of programming a target cell of the memory device includes activating selection transistors connected to a main string and substring of the target cell.
摘要翻译：非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。编程存储器件的目标单元的方法包括激活连接到目标单元的主串和子串的选择晶体管。

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