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1. 发明申请

US20080102595A1 ETCHING METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于制造半导体器件的蚀刻方法
公开(公告)号：US20080102595A1
公开(公告)日：2008-05-01
申请号：US11969105
申请日：2008-01-03
申请人： Won-Jun LEE , Byoung-Moon YOON , In-Seak HWANG , Yong-Sun KO
发明人： Won-Jun LEE , Byoung-Moon YOON , In-Seak HWANG , Yong-Sun KO
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L21/31111
摘要： A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.
摘要翻译：提供具有电介质层和从电介质层的顶表面部分突出的电极的晶片。用诸如LAL的化学溶液蚀刻电介质层。在蚀刻之前，电极的突出部分被去除或减少，以防止化学溶液中包含的任何气泡粘附到电极上。因此，化学溶液可以蚀刻介电层而不被包含在化学溶液中的任何气泡所阻挡。

2. 发明申请

US20160315019A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING A COMPOSITION FOR REMOVING PHOTORESIST AND METHODS OF REMOVING PHOTORESIST FROM A SEMICONDUCTOR SUBSTRATE 有权
标题翻译：使用组合物制造光电转换器的半导体器件的制造方法和从半导体衬底去除光电离器的方法
公开(公告)号：US20160315019A1
公开(公告)日：2016-10-27
申请号：US15084536
申请日：2016-03-30
申请人： Jung-Min OH , Mi-Hyun PARK , Hyo-San LEE , Ji-Hoon JEONG , Yong-Sun KO , In-Gi KIM , Na-Rim KIM , Sang-Tae KIM , Seong-Min KIM , Kyong-Ho LEE
发明人： Jung-Min OH , Mi-Hyun PARK , Hyo-San LEE , Ji-Hoon JEONG , Yong-Sun KO , In-Gi KIM , Na-Rim KIM , Sang-Tae KIM , Seong-Min KIM , Kyong-Ho LEE
IPC分类号： H01L21/8238 , H01L21/027 , H01L21/8234 , H01L29/16 , H01L21/311 , H01L21/02 , H01L21/3105 , G03F7/42 , H01L21/266
CPC分类号： G03F7/426 , G03F7/039 , G03F7/42 , G03F7/422 , G03F7/425 , H01L21/266 , H01L21/31133 , H01L21/823814 , H01L21/823828 , H01L29/16
摘要： A composition for removing photoresist, including an alkyl ammonium fluoride salt in an amount ranging from about 0.5 weight percent to about 10 weight percent, based on a total weight of the composition; an organic sulfonic acid in an amount ranging from about 1 weight percent to about 20 weight percent, based on the total weight of the composition; and a lactone-based solvent in an amount ranging from about 70 weight percent to about 98.5 weight percent, based on the total weight of the composition.
摘要翻译：基于组合物的总重量，用于除去光致抗蚀剂的组合物，其包含约0.5重量％至约10重量％的烷基铵氟化物盐; 基于组合物的总重量的约1重量％至约20重量％的量的有机磺酸; 和基于组合物总重量的约70重量％至约98.5重量％的内酯类溶剂。

3. 发明申请

US20150176897A1 SEALING MEMBER AND SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME 有权
标题翻译：密封构件和基板加工装置，包括它们
公开(公告)号：US20150176897A1
公开(公告)日：2015-06-25
申请号：US14556969
申请日：2014-12-01
申请人： Yong-Myung JUN , Yong-Sun KO , Kun-Tack LEE , Il-Sang LEE , Ji-Hoon JEONG , Yong-Jhin CHO , Jin-Suk HONG
发明人： Yong-Myung JUN , Yong-Sun KO , Kun-Tack LEE , Il-Sang LEE , Ji-Hoon JEONG , Yong-Jhin CHO , Jin-Suk HONG
IPC分类号： F26B25/00 , F26B25/14 , F16J15/02
CPC分类号： F26B25/008 , C23C16/4409 , F16J15/022 , F26B25/14 , H01L21/67017 , H01L21/67028 , H01L21/67034
摘要： A sealing member includes a body having a ring shape, a lower contacting portion protruding from a lower end of the body and having at least one recess, the recess provided in a lower surface of the lower contacting portion and extending in a radial direction of the body, and an outer contacting portion protruding outwards from the body along an outer side portion of the body.
摘要翻译：密封构件包括具有环形的主体，从所述主体的下端突出的下接触部分，并且具有至少一个凹部，所述凹部设置在所述下接触部分的下表面中并沿着所述凹部的径向方向延伸主体和沿着身体的外侧部分从身体向外突出的外接触部分。

4. 发明申请

US20090206399A1 METHOD OF FORMING A RECESS CHANNEL TRENCH PATTERN, AND FABRICATING A RECESS CHANNEL TRANSISTOR 审中-公开
标题翻译：形成记忆通道图案的方法和制作记录道信道
公开(公告)号：US20090206399A1
公开(公告)日：2009-08-20
申请号：US12430831
申请日：2009-04-27
申请人： Jong-Chul PARK , Yong-Sun KO , Tae-Hyuk AHN
发明人： Jong-Chul PARK , Yong-Sun KO , Tae-Hyuk AHN
IPC分类号： H01L29/78
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/823412 , H01L21/823437 , H01L27/10808 , H01L27/10876
摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
摘要翻译：提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。掩模层可以被图案化为曲线型。在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

5. 发明申请

US20070148884A1 METHOD OF FORMING A RECESS CHANNEL TRENCH PATTERN, AND FABRICATING A RECESS CHANNEL TRANSISTOR 有权
标题翻译：形成记忆通道图案的方法和制作记录道信道
公开(公告)号：US20070148884A1
公开(公告)日：2007-06-28
申请号：US11682632
申请日：2007-03-06
申请人： Jong-Chul PARK , Yong-Sun KO , Tae-Hyuk AHN
发明人： Jong-Chul PARK , Yong-Sun KO , Tae-Hyuk AHN
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/823412 , H01L21/823437 , H01L27/10808 , H01L27/10876
摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
摘要翻译：提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。掩模层可以被图案化为曲线型。在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

6. 发明申请

US20070141834A1 LOCAL INTERCONNECTION METHOD AND STRUCTURE FOR USE IN SEMICONDUCTOR DEVICE 失效
标题翻译：局部互连方法和结构用于半导体器件
公开(公告)号：US20070141834A1
公开(公告)日：2007-06-21
申请号：US11679722
申请日：2007-02-27
申请人： Sung-Un KWON , Yong-Sun KO
发明人： Sung-Un KWON , Yong-Sun KO
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76808 , H01L21/76895
摘要： A local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern. The first etching mask pattern is then removed and a second etching mask pattern is formed so as to partially expose the insulation film provided within the recess pattern. The insulation film within the recess pattern is etched to form apertures for exposing a partial surface of the gate electrodes. The second etching mask pattern is then removed. The recess pattern and the apertures are then filled with conductive material to form a local interconnection layer for connecting between the gate electrodes.
摘要翻译：用于形成其的局部互连配线结构方法通过形成公共孔径来减小栅电极的局部互连层与有源区之间的短路的可能性，以便在局部互连层和有源区之间具有确定的孔径半导体衬底的绝缘膜。形成局部互连线的方法可以包括形成第一蚀刻掩模图案，其具有比形成在半导体衬底上并被绝缘膜覆盖的相邻栅电极的内端之间的长度的长度。蚀刻掩模同时具有与栅电极的外端之间的长度相同或更短的长度。随后蚀刻在第一蚀刻掩模图案中暴露的绝缘膜，使得绝缘膜保持高于栅电极的最高高度，以形成凹陷图案。然后去除第一蚀刻掩模图案，并且形成第二蚀刻掩模图案，以便部分地暴露设置在凹槽图案内的绝缘膜。蚀刻凹槽图形内的绝缘膜以形成用于暴露栅电极的局部表面的孔。然后去除第二蚀刻掩模图案。然后用导电材料填充凹槽图案和孔，以形成用于连接栅电极的局部互连层。

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