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1. 发明申请

US20090091975A1 Non-volatile memory device and operation method of the same 有权
标题翻译：非易失性存储器件及其操作方法相同
公开(公告)号：US20090091975A1
公开(公告)日：2009-04-09
申请号：US12081679
申请日：2008-04-18
申请人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
发明人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , H01L27/11521 , H01L27/11568
摘要： Provided are a non-volatile memory device and an operation method of the same. The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor.
摘要翻译：提供了一种非易失性存储器件及其操作方法。非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。

2. 发明授权

US07813180B2 Non-volatile memory devices and methods of operating the same 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US07813180B2
公开(公告)日：2010-10-12
申请号：US12005376
申请日：2007-12-27
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-hee Lee
IPC分类号： G11C7/00
CPC分类号： H01L29/7881 , G11C16/3418 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/66825
摘要： Example embodiment non-volatile memory devices may be capable of increased integration and reliability and may provide example methods of operating non-volatile memory devices. Example embodiment non-volatile memory devices may include a first control gate electrode on a semiconductor substrate. A first charge storing layer may be between the semiconductor substrate and the first control gate electrode. A source region may be defined in the semiconductor substrate at one side of the first control gate electrode. A first auxiliary gate electrode may be at the other side of the first control gate electrode and may be recessed into the semiconductor substrate. A first drain region may be defined in the semiconductor substrate at one side of the first auxiliary gate electrode opposite to the first control gate electrode. A bit line may be connected to the first drain region.
摘要翻译：示例性实施例非易失性存储器设备可能能够提高集成度和可靠性，并且可以提供操作非易失性存储器设备的示例性方法。示例性实施例非易失性存储器件可以包括半导体衬底上的第一控制栅电极。第一电荷存储层可以在半导体衬底和第一控制栅电极之间。源区域可以在第一控制栅电极的一侧的半导体衬底中限定。第一辅助栅电极可以在第一控制栅电极的另一侧，并且可以凹入到半导体衬底中。第一漏极区域可以在第一辅助栅电极的与第一控制栅电极相对的一侧的半导体衬底中限定。位线可以连接到第一漏区。

3. 发明申请

US20080175061A1 Non-volatile memory devices and methods of operating the same 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20080175061A1
公开(公告)日：2008-07-24
申请号：US12005376
申请日：2007-12-27
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-hee Lee
IPC分类号： G11C16/06 , H01L29/788
CPC分类号： H01L29/7881 , G11C16/3418 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/66825
摘要： Example embodiment non-volatile memory devices may be capable of increased integration and reliability and may provide example methods of operating non-volatile memory devices. Example embodiment non-volatile memory devices may include a first control gate electrode on a semiconductor substrate. A first charge storing layer may be between the semiconductor substrate and the first control gate electrode. A source region may be defined in the semiconductor substrate at one side of the first control gate electrode. A first auxiliary gate electrode may be at the other side of the first control gate electrode and may be recessed into the semiconductor substrate. A first drain region may be defined in the semiconductor substrate at one side of the first auxiliary gate electrode opposite to the first control gate electrode. A bit line may be connected to the first drain region.
摘要翻译：示例性实施例非易失性存储器设备可能能够提高集成度和可靠性，并且可以提供操作非易失性存储器设备的示例性方法。示例性实施例非易失性存储器件可以包括半导体衬底上的第一控制栅电极。第一电荷存储层可以在半导体衬底和第一控制栅电极之间。源区域可以在第一控制栅电极的一侧的半导体衬底中限定。第一辅助栅电极可以在第一控制栅电极的另一侧，并且可以凹入到半导体衬底中。第一漏极区域可以在第一辅助栅电极的与第一控制栅电极相对的一侧的半导体衬底中限定。位线可以连接到第一漏区。

4. 发明授权

US07796432B2 Non-volatile memory device and method of operating the same 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US07796432B2
公开(公告)日：2010-09-14
申请号：US12149213
申请日：2008-04-29
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon , Tae-hee Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C2213/71
摘要： A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.
摘要翻译：非易失性存储器件可以包括多个堆叠半导体层，多个NAND串，公共位线，公共源极线和/或多个串选择线。多个NAND串可以在多个半导体层上。多个NAND串中的每一个可以包括布置在NAND单元阵列中的多个存储单元和/或至少一个串选择晶体管。公共位线可以在存储器单元的第一端处共同连接到每个NAND串。公共源极线可以在存储器单元的第二端处共同连接到每个NAND串。多个串选择线可以耦合到包括在每个NAND串中的至少一个串选择晶体管，使得施加到公共位线的信号被选择性地施加到NAND串。

5. 发明授权

US07894265B2 Non-volatile memory device and operation method of the same 有权
标题翻译：非易失性存储器件及其操作方法相同
公开(公告)号：US07894265B2
公开(公告)日：2011-02-22
申请号：US12081679
申请日：2008-04-18
申请人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
发明人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
IPC分类号： G11C5/06 , G11C16/04 , G11C16/10 , G11C16/26
CPC分类号： G11C16/0483 , H01L27/11521 , H01L27/11568
摘要： The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor. A method of programming a target cell of the memory device includes activating selection transistors connected to a main string and substring of the target cell.
摘要翻译：非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。编程存储器件的目标单元的方法包括激活连接到目标单元的主串和子串的选择晶体管。

6. 发明申请

US20090122613A1 Non-volatile memory device and method of operating the same 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20090122613A1
公开(公告)日：2009-05-14
申请号：US12149213
申请日：2008-04-29
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon , Tae-hee Lee
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C16/10 , G11C2213/71
摘要： A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.
摘要翻译：非易失性存储器件可以包括多个堆叠半导体层，多个NAND串，公共位线，公共源极线和/或多个串选择线。多个NAND串可以在多个半导体层上。多个NAND串中的每一个可以包括布置在NAND单元阵列中的多个存储单元和/或至少一个串选择晶体管。公共位线可以在存储器单元的第一端处共同连接到每个NAND串。公共源极线可以在存储器单元的第二端处共同连接到每个NAND串。多个串选择线可以耦合到包括在每个NAND串中的至少一个串选择晶体管，使得施加到公共位线的信号被选择性地施加到NAND串。

7. 发明申请

US20080191264A1 Non-volatile memory devices and methods of operating and fabricating the same 审中-公开
标题翻译：非易失性存储器件及其操作和制造方法
公开(公告)号：US20080191264A1
公开(公告)日：2008-08-14
申请号：US12010139
申请日：2008-01-22
申请人： Won-Joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-hee Lee
发明人： Won-Joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-hee Lee
IPC分类号： H01L29/00 , H01L21/3205
CPC分类号： H01L27/115 , H01L27/11521
摘要： Non-volatile memory devices highly integrated using an oxide based compound semiconductor and methods of operating and fabricating the same are provided. A non-volatile memory device may include one or more oxide based compound semiconductor layers. A plurality of auxiliary gate electrodes may be arranged to be insulated from the one or more oxide based compound semiconductor layers. A plurality of control gate electrodes may be positioned between adjacent pairs of the plurality of auxiliary gate electrodes at a different level from the plurality of auxiliary gate electrodes. The plurality of control gate electrodes may be insulated from the one or more oxide based compound semiconductor layers. A plurality of charge storing layers may be interposed between the one or more oxide based compound semiconductor layers and the plurality of control gate electrodes.
摘要翻译：提供了使用基于氧化物的化合物半导体高度集成的非易失性存储器件及其操作和制造方法。非易失性存储器件可以包括一个或多个基于氧化物的化合物半导体层。多个辅助栅极电极可以布置成与一个或多个氧化物基化合物半导体层绝缘。多个控制栅电极可以位于与多个辅助栅极电极不同的多个辅助栅电极的相邻对之间。多个控制栅电极可以与一个或多个氧化物基化合物半导体层绝缘。可以在一个或多个氧化物基化合物半导体层和多个控制栅电极之间插入多个电荷存储层。

8. 发明申请

US20080157182A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080157182A1
公开(公告)日：2008-07-03
申请号：US11980632
申请日：2007-10-31
申请人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-Woong Hyun , Sung-jae Byun
发明人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-Woong Hyun , Sung-jae Byun
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/785 , H01L21/76897 , H01L29/41791 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7851 , H01L29/7881 , H01L29/792 , H01L2029/7858
摘要： Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.
摘要翻译：示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。半导体器件包括半导体衬底，半导体柱和接触插塞。半导体衬底包括至少一对使用（或功能）作为活性区的翅片。半导体柱可以插入翅片的部分之间以连接散热片。接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

9. 发明申请

US20080157176A1 Nonvolatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080157176A1
公开(公告)日：2008-07-03
申请号：US11902511
申请日：2007-09-21
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/42336 , H01L29/66803
摘要： A nonvolatile memory device having lower bit line contact resistance and a method of fabricating the same is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type may include first and second fins. A common bit line electrode may connect one end of the first fin to one end of the second fin. A plurality of control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode may be positioned between the common bit line electrode and the plurality of control gate electrodes. The first string selection gate electrode may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode may be positioned between the first string selection gate electrode and the plurality of control gate electrodes. The second string selection gate electrode may cover the first and second fins and expand across the top surface of each of the first and second fins. The first fin under the first string selection gate electrode and the second fin under the second string selection gate electrode may have a second conductivity type opposite to the first conductivity type.
摘要翻译：提供一种具有较低位线接触电阻的非易失性存储器件及其制造方法。在非易失性存储器件中，第一导电类型的半导体衬底可以包括第一和第二鳍片。公共位线电极可将第一鳍片的一端连接到第二鳍片的一端。多个控制栅极电极可以覆盖第一和第二鳍片并且跨越第一和第二鳍片中的每一个的顶表面膨胀。第一串选择栅极可以位于公共位线电极和多个控制栅电极之间。第一串选择栅电极可以覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。第二串选择栅电极可以位于第一串选择栅电极和多个控制栅电极之间。第二串选择栅电极可以覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。第一串选择栅电极下的第一鳍和第二串选择栅电极下的第二鳍可以具有与第一导电类型相反的第二导电类型。

10. 发明申请

US20080135916A1 Non-volatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080135916A1
公开(公告)日：2008-06-12
申请号：US11987008
申请日：2007-11-26
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/7885 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42344 , H01L29/42352 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： Provided are example embodiments of a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a control gate electrode arranged on a semiconductor substrate, a gate insulating layer interposed between the semiconductor substrate and the control gate electrode, a storage node layer interposed between the gate insulating layer and the control gate electrode, a blocking insulating layer interposed between the storage node layer and the control gate electrode, first dopant doping regions along a first side of the control gate electrode, and second dopant doping regions along a second side of the control gate electrode. The first dopant doping regions may alternate with the second dopant doping regions. Stated differently, each of the second dopant doping regions may be arranged in a region on the second side of the control gate electrode that is adjacent to one of the first dopant doping regions.
摘要翻译：提供了非易失性存储器件的示例性实施例及其制造方法。非易失性存储器件可以包括布置在半导体衬底上的控制栅电极，介于半导体衬底和控制栅电极之间的栅极绝缘层，介于栅极绝缘层和控制栅电极之间的存储节点层，插入在所述存储节点层和所述控制栅电极之间的阻挡绝缘层，沿着所述控制栅电极的第一侧的第一掺杂剂掺杂区域和沿着所述控制栅电极的第二侧的第二掺杂剂掺杂区域。第一掺杂剂掺杂区域可以与第二掺杂剂掺杂区域交替。换句话说，每个第二掺杂剂掺杂区域可以被布置在与第一掺杂剂掺杂区域中的一个相邻的控制栅电极的第二侧上的区域中。

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