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    • 10. 发明申请
    • Method for Manufacturing a Transistor of a Semiconductor Memory Device
    • 制造半导体存储器件的晶体管的方法
    • US20090093101A1
    • 2009-04-09
    • US12331830
    • 2008-12-10
    • Hyun Jung Kim
    • Hyun Jung Kim
    • H01L21/762
    • H01L29/7831H01L27/10823H01L27/10826H01L27/10844H01L29/7851
    • A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.
    • 一种半导体存储器件的晶体管,包括具有多个有源区和器件隔离区的半导体衬底,多个第一和第二沟槽器件隔离层,它们在半导体衬底的器件隔离区上相互交替布置 所述第一沟槽器件隔离层具有对应于较高台阶高度的第一厚度,并且所述第二沟槽器件隔离层具有对应于相对较低台阶高度的第二厚度,在每个所述有源区域中形成的凹陷区域由 预定深度在其边界部分处具有阶梯轮廓,所述凹陷区域的高度高于所述第二沟槽器件隔离层的高度,以在相邻的两个第二沟槽器件隔离层之间具有向上突出部分,栅极绝缘层和 形成在栅极绝缘层上的与栅极堆叠重叠的多个栅极堆叠 相应的活性区域的凸起轮廓和相关凹陷区域的突出部分。