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1. 发明授权

US07649191B2 Forming a carbon layer between phase change layers of a phase change memory 有权
标题翻译：在相变存储器的相变层之间形成碳层
公开(公告)号：US07649191B2
公开(公告)日：2010-01-19
申请号：US11899862
申请日：2007-09-07
申请人： Wolodymyr Czubatyj , Sergey Kostylev , Tyler A. Lowrey , Guy C. Wicker
发明人： Wolodymyr Czubatyj , Sergey Kostylev , Tyler A. Lowrey , Guy C. Wicker
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L27/2427 , H01L45/00 , H01L45/06 , H01L45/1253 , H01L45/1293 , H01L45/141
摘要： A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized region to a lower conductivity region. This region then causes the localization of heating and current flow through the upper phase change material layer. In some embodiments, less phase change material may be required to change phase to form a phase change memory, reducing the current requirements of the resulting phase change memory.
摘要翻译：含碳层可以形成在一对含硫族化物的含相变层的层之间。当下部硫族化物层允许电流通过时，可以在其中形成细丝。然后，细丝将含碳层的电加热定位，将相对局部化的区域转化为较低的导电性区域。该区域然后导致加热和电流流过上相变材料层的定位。在一些实施例中，可能需要较少的相变材料来改变相位以形成相变存储器，从而减少所得到的相变存储器的电流要求。

2. 发明授权

US07282730B2 Forming a carbon layer between phase change layers of a phase change memory 有权
标题翻译：在相变存储器的相变层之间形成碳层
公开(公告)号：US07282730B2
公开(公告)日：2007-10-16
申请号：US11037850
申请日：2005-01-18
申请人： Wolodymyr Czubatyj , Sergey Kostylev , Tyler A. Lowrey , Guy C. Wicker
发明人： Wolodymyr Czubatyj , Sergey Kostylev , Tyler A. Lowrey , Guy C. Wicker
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L27/2427 , H01L45/00 , H01L45/06 , H01L45/1253 , H01L45/1293 , H01L45/141
摘要： A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized region to a lower conductivity region. This region then causes the localization of heating and current flow through the upper phase change material layer. In some embodiments, less phase change material may be required to change phase to form a phase change memory, reducing the current requirements of the resulting phase change memory.
摘要翻译：含碳层可以形成在一对含硫族化物的含相变层的层之间。当下部硫族化物层允许电流通过时，可以在其中形成细丝。然后，细丝将含碳层的电加热定位，将相对局部化的区域转化为较低的导电性区域。该区域然后导致加热和电流流过上相变材料层的定位。在一些实施例中，可能需要较少的相变材料来改变相位以形成相变存储器，从而减少所得到的相变存储器的电流要求。

3. 发明授权

US07589364B2 Electrically rewritable non-volatile memory element and method of manufacturing the same 有权
标题翻译：电可重写非易失性存储元件及其制造方法
公开(公告)号：US07589364B2
公开(公告)日：2009-09-15
申请号：US11264129
申请日：2005-11-02
申请人： Isamu Asano , Natsuki Sato , Tyler A. Lowrey , Guy C. Wicker , Wolodymyr Czubatyj , Stephen J. Hudgens
发明人： Isamu Asano , Natsuki Sato , Tyler A. Lowrey , Guy C. Wicker , Wolodymyr Czubatyj , Stephen J. Hudgens
IPC分类号： H01L31/112
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148
摘要： A non-volatile memory element includes a first interlayer insulation layer 11 having a first through-hole 11a, a second interlayer insulation layer 12 having a second through-hole 12a formed on the first interlayer insulation layer 11, a bottom electrode 13 provided in the first through-hole 11, recording layer 15 containing phase change material provided in the second through-hole 12, a top electrode 16 provided on the second interlayer insulation layer 12, and a thin-film insulation layer 14 formed between the bottom electrode 13 and the recording layer 15. In accordance with this invention, the diameter D1 of a bottom electrode 13 buried in a first through-hole 11a is smaller than the diameter D2 of a second through-hole 12a, thereby decreasing the thermal capacity of the bottom electrode 13. Therefore, when a pore 14a is formed by dielectric breakdown in a thin-film insulation layer 14 and the vicinity is used as a heating region, the amount of heat escaping to the bottom electrode 13 is decreased, resulting in higher heating efficiency.
摘要翻译：非易失性存储元件包括具有第一通孔11a的第一层间绝缘层11，形成在第一层间绝缘层11上的第二通孔12a的第二层间绝缘层12，第一通孔11，设置在第二通孔12中的包含相变材料的记录层15，设置在第二层间绝缘层12上的顶部电极16和形成在底部电极13和记录层15.根据本发明，埋在第一通孔11a中的底部电极13的直径D1小于第二通孔12a的直径D2，从而降低底部电极的热容量因此，当通过薄膜绝缘层14中的电介质击穿形成孔14a并且将其附近用作加热区域时，向底部电极逸出的热量 13降低，导致更高的加热效率。

4. 发明申请

US20080273379A1 Programming a normally single phase chalcogenide material for use as a memory of FPLA 有权
标题翻译：编程正常的单相硫族化物材料，用作FPLA的记忆
公开(公告)号：US20080273379A1
公开(公告)日：2008-11-06
申请号：US12218122
申请日：2008-07-11
申请人： George A. Gordon , Ward D. Parkinson , John M. Peters , Tyler A. Lowrey , Stanford Ovshinsky , Guy C. Wicker , Ilya V. Karpov , Charles C. Kuo
发明人： George A. Gordon , Ward D. Parkinson , John M. Peters , Tyler A. Lowrey , Stanford Ovshinsky , Guy C. Wicker , Ilya V. Karpov , Charles C. Kuo
IPC分类号： G11C11/00 , H01L21/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2013/0092 , G11C2213/77 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.
摘要翻译：可以用稳定的硫属化物玻璃来实现记忆，硫化物玻璃被定义为当暴露于200℃下30分钟或更短时不改变为通常结晶相的通常为非晶态的硫族化物材料。可以通过改变材料的阈值电压来编程不同的状态。可以用不同幅度和/或不同脉冲下降时间的脉冲来改变阈值电压。可以使用两种不同状态的阈值电压之间的参考电平进行读取。通常不需要单独的访问设备。

5. 发明授权

US07414883B2 Programming a normally single phase chalcogenide material for use as a memory or FPLA 有权
标题翻译：编程正常的单相硫族化物材料，用作记忆体或FPLA
公开(公告)号：US07414883B2
公开(公告)日：2008-08-19
申请号：US11407573
申请日：2006-04-20
申请人： George A. Gordon , Ward D. Parkinson , John M. Peters , Tyler A. Lowrey , Stanford Ovshinsky , Guy C. Wicker , Ilya V. Karpov , Charles C. Kuo
发明人： George A. Gordon , Ward D. Parkinson , John M. Peters , Tyler A. Lowrey , Stanford Ovshinsky , Guy C. Wicker , Ilya V. Karpov , Charles C. Kuo
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2013/0092 , G11C2213/77 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.
摘要翻译：可以用稳定的硫属化物玻璃来实现记忆，硫化物玻璃被定义为当暴露于200℃下30分钟或更短时不改变为通常结晶相的通常为非晶态的硫族化物材料。可以通过改变材料的阈值电压来编程不同的状态。可以用不同幅度和/或不同脉冲下降时间的脉冲来改变阈值电压。可以使用两种不同状态的阈值电压之间的参考电平进行读取。通常不需要单独的访问设备。

6. 发明授权

US07864567B2 Programming a normally single phase chalcogenide material for use as a memory of FPLA 有权
标题翻译：编程正常的单相硫族化物材料，用作FPLA的记忆
公开(公告)号：US07864567B2
公开(公告)日：2011-01-04
申请号：US12218122
申请日：2008-07-11
申请人： George A. Gordon , Ward D. Parkinson , John M. Peters , Tyler A. Lowrey , Stanford Ovshinsky , Guy C. Wicker , Ilya V. Karpov , Charles C. Kuo
发明人： George A. Gordon , Ward D. Parkinson , John M. Peters , Tyler A. Lowrey , Stanford Ovshinsky , Guy C. Wicker , Ilya V. Karpov , Charles C. Kuo
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2013/0092 , G11C2213/77 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.
摘要翻译：可以用稳定的硫属化物玻璃来实现记忆，硫化物玻璃被定义为当暴露于200℃下30分钟或更短时不改变为通常结晶相的通常为非晶态的硫族化物材料。可以通过改变材料的阈值电压来编程不同的状态。可以用不同幅度和/或不同脉冲下降时间的脉冲来改变阈值电压。可以使用两种不同状态的阈值电压之间的参考电平进行读取。通常不需要单独的访问设备。

7. 发明授权

US06673700B2 Reduced area intersection between electrode and programming element 有权
标题翻译：电极与编程元件之间的减少交点
公开(公告)号：US06673700B2
公开(公告)日：2004-01-06
申请号：US09895020
申请日：2001-06-30
申请人： Charles H. Dennison , Guy C. Wicker , Tyler A. Lowrey , Stephen J. Hudgens , Chien Chiang , Daniel Xu
发明人： Charles H. Dennison , Guy C. Wicker , Tyler A. Lowrey , Stephen J. Hudgens , Chien Chiang , Daniel Xu
IPC分类号： H01L21326
CPC分类号： H01L27/2463 , G11C13/0004 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A method comprising forming a sacrificial layer over less than the entire portion of a contact area on a substrate, the sacrificial layer having a thickness defining an edge over the contact area, forming a spacer layer over the spacer, the spacer layer conforming to the shape of the first sacrificial layer such that the spacer layer comprises an edge portion over the contact area adjacent the first sacrificial layer edge, removing the sacrificial layer, while retaining the edge portion of the spacer layer over the contact area, forming a dielectric layer over the contact area, removing the edge portion, and forming a programmable material to the contact area formerly occupied by the edge portion. An apparatus comprising a volume of programmable material, a conductor, and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area at one end coupled to the volume of programmable material, wherein the contact area is less than the surface area at the one end.
摘要翻译：一种方法，包括在小于衬底上的接触区域的整个部分上形成牺牲层，所述牺牲层具有限定在所述接触区域上的边缘的厚度，在所述间隔物上形成间隔层，所述隔离层符合形状的第一牺牲层，使得间隔层包括邻近第一牺牲层边缘的接触区域上的边缘部分，去除牺牲层，同时将间隔物层的边缘部分保持在接触区域上方，形成介于第接触区域，去除边缘部分，并且将可编程材料形成到以前由边缘部分占据的接触区域。一种包括可编程材料体积，导体和设置在所述可编程材料体积与所述导体之间的电极的装置，所述电极在一端与所述可编程材料的体积相连接的接触区域，其中所述接触面积小于一端的表面积。

8. 发明申请

US20090298224A1 Memory and Access Device and Method Therefor 有权
标题翻译：内存和访问设备及其方法
公开(公告)号：US20090298224A1
公开(公告)日：2009-12-03
申请号：US12538904
申请日：2009-08-11
申请人： Tyler A. Lowrey
发明人： Tyler A. Lowrey
IPC分类号： H01L21/06
CPC分类号： H01L27/2427 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L45/1675
摘要： Briefly, in accordance with an embodiment of the invention, a memory and a method to manufacture the memory is provided. The memory may include a phase change material over a substrate. The memory may further include a switching material coupled to the phase change material, wherein the switching material comprises a chalcogen other than oxygen and wherein the switching material and the phase change material form portions of a vertical structure over the substrate.
摘要翻译：简而言之，根据本发明的实施例，提供了一种用于制造存储器的存储器和方法。存储器可以包括在衬底上的相变材料。存储器还可以包括耦合到相变材料的开关材料，其中开关材料包括除氧以外的硫族元素，并且其中开关材料和相变材料在衬底上形成垂直结构的部分。

9. 发明授权

US07563666B2 Semiconductor structures including vertical diode structures and methods of making the same 失效
标题翻译：包括垂直二极管结构的半导体结构及其制造方法
公开(公告)号：US07563666B2
公开(公告)日：2009-07-21
申请号：US11869012
申请日：2007-10-09
申请人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
发明人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
IPC分类号： H01L21/8234
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L27/0814 , H01L27/101 , H01L27/1021 , H01L27/24 , H01L29/6609 , H01L29/66136 , H01L29/861 , H01L45/04 , H01L45/145 , Y10S257/903 , Y10S257/91 , Y10S438/979
摘要： Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
摘要翻译：提供了制造垂直二极管结构的半导体结构和方法。垂直二极管结构可以具有延伸穿过绝缘层并接触硅晶片上的有源区的二极管开口。硅化钛层可以形成在二极管开口的内表面上并与活性区接触。二极管开口最初可以填充非晶硅插塞，其在沉积期间被掺杂并随后重结晶以形成大晶粒多晶硅。硅插头具有可以重掺杂第一类型掺杂剂的顶部部分和可以轻掺杂第二类型掺杂剂的底部部分。顶部可以由底部限定，以便不与硅化钛层接触。在垂直二极管结构的一个实施例中，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

10. 发明授权

US07547935B2 Semiconductor devices including buried digit lines that are laterally offset from corresponding active-device regions 有权
标题翻译：半导体器件包括从相应的有源器件区域横向偏移的埋置数字线
公开(公告)号：US07547935B2
公开(公告)日：2009-06-16
申请号：US10920938
申请日：2004-08-17
申请人： Tyler A. Lowrey
发明人： Tyler A. Lowrey
IPC分类号： H01L29/76 , H01L23/48
CPC分类号： H01L21/76897 , H01L21/76838 , H01L27/105 , H01L27/1052 , H01L27/10811 , H01L27/10885 , H01L27/10888
摘要： A method of electrically linking contacts of a semiconductor device to their corresponding digit lines. The method includes disposing a quantity of mask material into a trench through which the contact is exposed. The mask also abuts a connect region of a conductive element of a corresponding digit line and, therefore, protrudes somewhat over a surface of the semiconductor device. A layer of insulative material is disposed over the semiconductor device with the mask material being exposed therethrough. The mask material is then removed, leaving open cavities that include the trench and a strap region continuous with the trench and with a connect region of the corresponding digit line. Conductive material is disposed within the cavity and electrically isolated from conductive material disposed in adjacent cavities, which define conductive plugs or studs and conductive straps from the conductive material. These plugs or studs and straps provide an electrically conductive link between each contact of the semiconductor device and its corresponding digit line. Semiconductor devices that include features that have been fabricated in accordance with the method of the present invention are also within the scope of the present invention.
摘要翻译：一种将半导体器件的触点电连接到其对应的数字线的方法。该方法包括将一定量的掩模材料设置在暴露于触点的沟槽中。掩模还邻接相应数字线的导电元件的连接区域，因此在半导体器件的表面上略微突出。绝缘材料层设置在半导体器件上，掩模材料暴露在其中。然后去除掩模材料，留下包括沟槽的开放空腔和与沟槽连续的带区域以及相应数字线的连接区域。导电材料设置在空腔内并与设置在相邻空腔中的导电材料电绝缘，其从导电材料限定导电塞或螺栓和导电带。这些插头或螺柱和带在半导体器件的每个触点与其对应的数字线之间提供导电连接。包括根据本发明的方法制造的特征的半导体器件也在本发明的范围内。

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