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1. 发明授权

US06576948B2 Integrated circuit configuration and method for manufacturing it 有权
标题翻译：集成电路配置及其制造方法
公开(公告)号：US06576948B2
公开(公告)日：2003-06-10
申请号：US09873231
申请日：2001-06-04
申请人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L27/108
摘要： An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.
摘要翻译：集成电路包含平面第一晶体管和二极管。二极管连接在第一晶体管的第一源极/漏极区域和第一晶体管的栅电极之间，使得电荷被阻止从栅电极放电到第一源极/漏极区域。作为二极管的一部分的二极管层设置在第一源极/漏极区域的一部分上。作为二极管的附加部分的导电结构设置在栅电极的一部分上方并且设置在二极管层上。二极管可以配置为隧道二极管。二极管层可以通过热氧化生产。制造二极管只需要一个掩模。电容器可以设置在二极管的上方。电容器的第一电容器电极连接到导电结构。

2. 发明授权

US06521935B2 Mos transistor and dram cell configuration 有权
标题翻译：莫斯晶体管和电池组配置
公开(公告)号：US06521935B2
公开(公告)日：2003-02-18
申请号：US10027524
申请日：2001-12-26
申请人： Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876 , H01L29/66666 , H01L29/7841 , H01L29/78642
摘要： A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.
摘要翻译： MOS晶体管包括上层堆叠的上源极/漏极区，沟道区和下源极/漏极区，并且形成衬底的突起。栅极电介质邻接突起的第一横向区域。栅电极邻接栅极电介质。导电结构在通道区域的区域中毗邻突起的第二横向区域。导电结构邻接栅电极。

3. 发明授权

US06399433B2 Method for fabricating a memory cell 有权
标题翻译：用于制造存储单元的方法
公开(公告)号：US06399433B2
公开(公告)日：2002-06-04
申请号：US09773218
申请日：2001-01-31
申请人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/55
摘要： A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The-layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.
摘要翻译：一种存储单元的制造方法包括在半导体本体上形成多晶硅层，该多晶硅层具有设置在第一平面中的至少一个选择晶体管。在层的两个相邻结构之间形成间隙，并且该层的相邻结构之一被放置在第一硅插头的表面上。在该间隙中形成单元板电极，并在该层中形成沟槽。沟槽达到第一插头表面的最远处，并且填充有绝缘层。该层被删除。形成具有高ε或铁电介质的存储电容器和存储节点电极。电容器设置在身体内和上方的第二平面内。绝缘层被硅替代以形成直接连接到第一插头的第二硅插头。第二插头电连接到存储节点电极，第一平面通过第一和第二插头电连接到第二平面。

4. 发明授权

US06442065B1 Method for operating a memory cell configuration having dynamic gain memory cells 有权
标题翻译：用于操作具有动态增益存储单元的存储单元配置的方法
公开(公告)号：US06442065B1
公开(公告)日：2002-08-27
申请号：US09935356
申请日：2001-08-22
申请人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： G11C1140
CPC分类号： G11C11/404 , G11C11/4023
摘要： Each memory cell of a cell configuration includes at least one memory transistor. To write first or second information on the memory cell, a gate electrode of the memory transistor is charged such that a first voltage or a second voltage is applied in the memory transistor. A reading voltage is applied in a second source/drain area of the memory transistor to read first information and second information respectively. The first voltage is applied between the second voltage and the reading voltage. The reading voltage is applied between the first voltage less a threshold voltage of the memory transistor and the second voltage less the threshold voltage of the memory transistor.
摘要翻译：单元结构的每个存储单元包括至少一个存储晶体管。为了在存储单元上写入第一或第二信息，对存储晶体管的栅电极进行充电，使得在存储晶体管中施加第一电压或第二电压。在存储晶体管的第二源极/漏极区域中施加读取电压以分别读取第一信息和第二信息。第一电压施加在第二电压和读取电压之间。读取电压施加在较低存储晶体管的阈值电压的第一电压和小于存储晶体管的阈值电压的第二电压之间。

5. 发明授权

US06608340B1 Substrate assembly having a depression suitable for an integrated circuit configuration and method for its fabrication 有权
标题翻译：具有适于集成电路结构的凹陷的衬底组件及其制造方法
公开(公告)号：US06608340B1
公开(公告)日：2003-08-19
申请号：US09821853
申请日：2001-03-30
申请人： Franz Hofmann , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Till Schlösser , Josef Willer
IPC分类号： H01L2972
CPC分类号： H01L27/10864
摘要： A depression extends from a main surface of the substrate to the inside of said substrate and has an upper area and an adjacent lower area. A cross-section of the upper area, parallel to the main surface, is provided with at least one corner. A cross-section of the lower area, parallel to the main surface, matches the cross-section of the upper area, particularly in the vicinity the upper area, with the following difference: each corner is rounded, whereby the cross section of the lower area is smaller than the cross-section of the upper area. In order to produce the indentation, the upper area is provided with an auxiliary spacer that is rounded by isotropic etching. The lower area is produced by selectively etching the substrate to form an auxiliary spacer.
摘要翻译：凹陷从基板的主表面延伸到所述基板的内部，并且具有上部区域和相邻的下部区域。平行于主表面的上部区域的横截面设置有至少一个角部。平行于主表面的下部区域的横截面与上部区域的横截面特别是在上部区域附近匹配，具有以下差异：每个角都是圆形的，由此下部区域的横截面面积小于上部区域的横截面。为了产生凹陷，上部区域设置有通过各向同性蚀刻而被圆化的辅助间隔件。通过选择性地蚀刻基板以形成辅助间隔物来产生下部区域。

6. 发明授权

US06538273B2 Ferroelectric transistor and method for fabricating it 有权
标题翻译：铁电晶体管及其制造方法
公开(公告)号：US06538273B2
公开(公告)日：2003-03-25
申请号：US09849910
申请日：2001-05-04
申请人： Josef Willer , Georg Braun , Till Schlösser , Thomas Haneder
发明人： Josef Willer , Georg Braun , Till Schlösser , Thomas Haneder
IPC分类号： H01L2902
CPC分类号： H01L29/78391
摘要： A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic intermediate layer is disposed on the surface of the channel region and forms a Schottky diode with the semiconductor substrate, and a ferroelectric layer and a gate electrode are disposed on its surface. The ferroelectric transistor is fabricated using steps appertaining to silicon process technology.
摘要翻译：公开了具有两个源极/漏极区域和设置在半导体衬底之间的沟道区域的铁电晶体管。金属中间层设置在沟道区域的表面上，并与半导体衬底形成肖特基二极管，并且在其表面上设置铁电层和栅电极。铁电晶体管使用与硅工艺技术相关的步骤制造。

7. 发明授权

US06504200B2 DRAM cell configuration and fabrication method 有权
公开(公告)号：US06504200B2
公开(公告)日：2003-01-07
申请号：US09951243
申请日：2001-09-12
申请人： Till Schlösser , Bernhard Sell , Josef Willer
发明人： Till Schlösser , Bernhard Sell , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823
摘要： Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend downwards into the trenches and which are arranged above the bit lines. The transistors are vertical transistors whose source/drain regions are located below the word lines and between adjacent trenches. The capacitors are linked with the upper source/drain regions. Conductive structures that surround the word lines from the top and the sides while being insulated from the word lines and bordering on the upper source/drain regions can link the upper source/drain regions with the capacitors.

8. 发明授权

US06642565B2 Miniaturized capacitor with solid-state dielectric, in particular for integrated semiconductor memories, E.G. DRAMS, and method for fabricating such a capacitor 有权
公开(公告)号：US06642565B2
公开(公告)日：2003-11-04
申请号：US09935624
申请日：2001-08-23
申请人： Emmerich Bertagnolli , Till Schlösser , Josef Willer
发明人： Emmerich Bertagnolli , Till Schlösser , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L28/82
摘要： A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface of a electrode body. The graining of the tungsten silicide layer is formed by tempering a temporarily present double layer that is formed of an understoichiometric tungsten silicide layer and a silicon layer. The double layer is formed on the tungsten silicide layer.

9. 发明授权

US06566187B1 DRAM cell system and method for producing same 有权
标题翻译： DRAM单元系统及其制造方法
公开(公告)号：US06566187B1
公开(公告)日：2003-05-20
申请号：US09806614
申请日：2001-05-11
申请人： Josef Willer , Franz Hoffmann , Till Schlösser
发明人： Josef Willer , Franz Hoffmann , Till Schlösser
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： DRAM cell arrangement and method for fabricating it Word lines and bit lines are arranged above a main area of a substrate, with the result that they have a planar construction and can be produced together with gate electrodes of transistors of a periphery of the cell arrangement. A depression of the substrate is provided per memory cell, a storage node of a storage capacitor being arranged in the lower region of said depression and a gate electrode of a vertical transistor being arranged in the upper region of said depression. The depressions of the memory cells are arranged between trenches filled with isolating structures. Upper source/drain regions of the transistors are arranged between two mutually adjacent isolating structures and between two mutually adjacent depressions. Lower source/drain regions are arranged in the substrate and adjoin the storage nodes. For process steps, alignment tolerances are so large that the space requirement for the memory cell can amount to 4F2.
摘要翻译： DRAM单元布置及其制造方法字线和位线布置在基板的主区域上方，结果是它们具有平面结构，并且可以与单元布置的外围的晶体管的栅电极一起生成。每个存储单元提供基板的凹陷，存储电容器的存储节点布置在所述凹陷的下部区域中，并且垂直晶体管的栅电极布置在所述凹陷的上部区域中。存储单元的凹陷布置在填充有隔离结构的沟槽之间。晶体管的上部源极/漏极区域布置在两个相互相邻的隔离结构之间以及两个彼此相邻的凹陷之间。下部源极/漏极区域布置在衬底中并与存储节点相邻。对于工艺步骤，对准公差如此大，使得存储器单元的空间需求可以达到4F2。

10. 发明授权

US06448600B1 DRAM cell configuration and fabrication method 失效
标题翻译： DRAM单元配置和制造方法
公开(公告)号：US06448600B1
公开(公告)日：2002-09-10
申请号：US09713484
申请日：2000-11-15
申请人： Till Schlösser , Franz Hofmann , Josef Willer
发明人： Till Schlösser , Franz Hofmann , Josef Willer
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10876 , H01L27/10888
摘要： The memory cells each have a capacitor and a transistor. A storage node of the capacitor is arranged in a first depression formed in a substrate. A gate electrode of the transistor is arranged in a second depression at a first lateral surface of the second depression. The second depression is spaced apart from the first depression. An upper source/drain region of the transistor adjoins the storage node and the second depression. A lower source/drain region of the transistor is formed deeper in the substrate than the upper source/drain region and it adjoins the second depression.
摘要翻译：存储单元各自具有电容器和晶体管。电容器的存储节点布置在形成在基板中的第一凹部中。晶体管的栅极布置在第二凹陷处的第二凹陷处的第二凹陷处的第一侧表面处。第二凹陷与第一凹陷间隔开。晶体管的上源极/漏极区域与存储节点和第二凹陷相邻。晶体管的下源极/漏极区域在衬底中比上部源极/漏极区域形成得更深，并且与第二凹陷相邻。

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