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1. 发明授权

US06865707B2 Test data generator 失效
标题翻译：测试数据生成器
公开(公告)号：US06865707B2
公开(公告)日：2005-03-08
申请号：US10109657
申请日：2002-04-01
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Luepke , Jochen Mueller , Peter Poechmueller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Luepke , Jochen Mueller , Peter Poechmueller , Michael Schittenhelm
IPC分类号： G01R31/3183 , G11C29/14 , G11C29/36 , G01R31/28 , G06F11/00
CPC分类号： G11C29/14 , G01R31/3183 , G11C29/36
摘要： Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock frequency of an input clock signal received by a test unit with a specific clock frequency multiplication factor. Also provided is a plurality of data registers for storing test data words read from the data registers, and multiplexer that switches through a test data word read from a data register with the high clock frequency of the output clock signal to a data bus in a way dependent on a register selection control datum of a multi-position register selection control data vector.
摘要翻译：用于产生用于测试具有倍频电路的电路的测试数据模式的测试数据发生器，其增加由测试单元以特定时钟倍频因子接收的输入时钟信号的低时钟频率。还提供了多个数据寄存器，用于存储从数据寄存器读取的测试数据字，以及多路复用器，以一种方式将通过从输出时钟信号的高时钟频率从数据寄存器读取的测试数据字切换到数据总线取决于多位置寄存器选择控制数据向量的寄存器选择控制基准。

2. 发明授权

US06744272B2 Test circuit 失效
标题翻译：测试电路
公开(公告)号：US06744272B2
公开(公告)日：2004-06-01
申请号：US10100504
申请日：2002-03-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Luepke , Jochen Mueller , Peter Poechmueller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Luepke , Jochen Mueller , Peter Poechmueller , Michael Schittenhelm
IPC分类号： G01R3128
CPC分类号： G11C29/48
摘要： A test circuit is adapted to test circuits having a high-frequency clock signal. The test circuit is positioned between a conventional tester and the circuit to be tested. The test circuit includes a frequency multiplication circuit which multiplies the clock signal of the conventional tester to produce a high-frequency clock signal. The test circuit also receives control signals from the conventional tester. The control signals are output to the circuit to be tested via a bus.
摘要翻译：测试电路适用于测试具有高频时钟信号的电路。测试电路位于常规测试仪和待测电路之间。测试电路包括一个倍频电路，它将传统测试仪的时钟信号相乘以产生高频时钟信号。测试电路还接收来自常规测试仪的控制信号。控制信号通过总线输出到要测试的电路。

3. 发明授权

US06618305B2 Test circuit for testing a circuit 有权
标题翻译：用于测试电路的测试电路
公开(公告)号：US06618305B2
公开(公告)日：2003-09-09
申请号：US10137125
申请日：2002-05-02
申请人： Wolfgang Ernst , Gunnar Krause , Peter Poechmueller , Justus Kuhn , Jens Luepke , Jochen Mueller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Peter Poechmueller , Justus Kuhn , Jens Luepke , Jochen Mueller , Michael Schittenhelm
IPC分类号： G11C700
CPC分类号： G11C29/48 , G01R31/31917 , G01R31/31926
摘要： Test circuit for testing a circuit to be tested, having a test data generator, which generates test data in a manner dependent on data control signals which are received via data control lines from an external test unit, a data output driver for outputting the generated test data via data line pairs of a differential data bus to the circuit to be tested, a data input circuit for receiving data that are read from the circuit to be tested and transmitted via the data line pairs of the differential data bus, a data comparison circuit, which compares the generated data and the read-out data and, in a manner depend at on the comparison result transmits an indication signal, which indicates whether the circuit to be tested is functional, to the external test unit via an indication signal line.
摘要翻译：用于测试要测试的电路的测试电路，具有测试数据发生器，其以取决于经由数据控制线从外部测试单元接收的数据控制信号的方式产生测试数据，用于输出所产生的测试的数据输出驱动器通过差分数据总线的数据线对与要测试的电路的数据的数据输入电路，用于接收经由差分数据总线的数据线对被测试和发送的电路读取的数据的数据输入电路，数据比较电路，其比较生成的数据和读出的数据，并且以取决于比较结果的方式，经由指示信号线将指示要测试的电路的指示信号发送到外部测试单元。

4. 发明授权

US06957373B2 Address generator for generating addresses for testing a circuit 失效
标题翻译：用于生成用于测试电路的地址的地址发生器
公开(公告)号：US06957373B2
公开(公告)日：2005-10-18
申请号：US10092129
申请日：2002-03-06
申请人： Wolfgang Ernst , Justus Kuhn , Jens Luepke , Peter Poechmüller , Gunnar Krause , Jochen Mueller , Michael Schittenhelm
发明人： Wolfgang Ernst , Justus Kuhn , Jens Luepke , Peter Poechmüller , Gunnar Krause , Jochen Mueller , Michael Schittenhelm
IPC分类号： G11C29/20 , G01R31/28 , G06F11/00 , G06F12/00 , G06F12/02 , G06F12/04
CPC分类号： G11C29/20
摘要： An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base address register can be assigned an associated offset register group having a plurality of offset registers for buffer-storing relative address values. Further, the address generator can include a first multiplexer circuit which is dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected to the circuit to be tested. A second multiplexer circuit can be dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which is dependent on an offset register selection control signal.
摘要翻译：提供地址发生器用于产生用于测试可寻址电路的地址。地址生成器可以包括用于缓冲存储基地址的基地址寄存器。可以为基地址寄存器分配具有多个偏移寄存器的相关联的偏移寄存器组，用于缓冲存储相对地址值。此外，地址生成器可以包括依赖于基本寄存器选择控制信号的第一多路复用器电路，将存储在基地址寄存器中的地址缓冲器切换到加法电路的第一输入和地址总线，地址总线连接到要测试的电路。第二多路复用器电路可以依赖于基本寄存器选择控制信号，将与连接的基地址寄存器相关联的偏移寄存器组连接到第三多路复用器电路，该第三多路复用器电路取决于偏移寄存器选择控制信号。

5. 发明授权

US07117404B2 Test circuit for testing a synchronous memory circuit 有权
标题翻译：用于测试同步存储器电路的测试电路
公开(公告)号：US07117404B2
公开(公告)日：2006-10-03
申请号：US10106414
申请日：2002-03-26
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Peter Poechmüller , Jochen Mueller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Peter Poechmüller , Jochen Mueller , Michael Schittenhelm
IPC分类号： G11C29/00
CPC分类号： G11C29/48
摘要： Test circuit for testing a synchronous memory circuit having a frequency multiplication circuit which multiplies a clock frequency of a low-frequency clock signal received from an external test unit by a particular frequency multiplication factor a test data generator which produces test data on the basis of data control signals received from the external test unit and outputs them to a data output driver a first signal delay circuit for delaying the test data which are output by the test data generator by an adjustable first delay time, a second signal delay circuit for delaying data which are read out of the synchronous memory circuit and are received by a data input driver in the test circuit by an adjustable second delay time, and having a data comparison circuit which compares the test data produced by the test data generator with the data read out of the memory circuit and, on the basis of the comparison result, outputs an indicator signal to the external test unit which indicates whether the synchronous memory circuit to be tested is operable.
摘要翻译：用于测试具有倍频电路的同步存储电路的测试电路，该倍频电路将从外部测试单元接收的低频时钟信号的时钟频率乘以特定的倍频因子，该测试数据生成器基于数据产生测试数据从外部测试单元接收的控制信号并将它们输出到数据输出驱动器第一信号延迟电路，用于将由测试数据发生器输出的测试数据延迟可调节的第一延迟时间;第二信号延迟电路，用于延迟数据，从同步存储器电路中读出并由测试电路中的数据输入驱动器接收可调节的第二延迟时间，并具有数据比较电路，该数据比较电路将由测试数据发生器产生的测试数据与从存储器电路，并且基于比较结果，向指示的外部测试单元输出指示符信号 s被测试的同步存储器电路是否可操作。

6. 发明授权

US07062690B2 System for testing fast synchronous digital circuits, particularly semiconductor memory chips 失效
公开(公告)号：US07062690B2
公开(公告)日：2006-06-13
申请号：US09907786
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G01R31/31905 , G11C29/56
摘要： A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.

7. 发明授权

US06862702B2 Address counter for addressing synchronous high-frequency digital circuits, in particular memory devices 失效
标题翻译：地址计数器用于寻址同步高频数字电路，特别是存储器件
公开(公告)号：US06862702B2
公开(公告)日：2005-03-01
申请号：US09907776
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： G11C29/56 , G11C29/00
CPC分类号： G11C29/56
摘要： The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.
摘要翻译：新颖的地址计数器可以与用于测试数字电路的现有测试单元结合使用 - 用于寻址同步高频数字电路，特别是快速存储器件。在可编程偏移寄存器中提供地址偏移值，其中多路复用器电路和选择和组合电路基于由测试单元以低频和并联馈送的输入信号。可以以非常灵活的方式在高时钟频率下实现简单的地址改变和地址跳转。

8. 发明授权

US06556492B2 System for testing fast synchronous semiconductor circuits 失效
公开(公告)号：US06556492B2
公开(公告)日：2003-04-29
申请号：US09907695
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： G11C700
CPC分类号： G11C29/56
摘要： The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

9. 发明授权

US06721904B2 System for testing fast integrated digital circuits, in particular semiconductor memory modules 失效
标题翻译：用于测试快速集成数字电路的系统，特别是半导体存储器模块
公开(公告)号：US06721904B2
公开(公告)日：2004-04-13
申请号：US09907693
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： H02H305
CPC分类号： G11C29/12015 , G11C29/48 , G11C29/56012
摘要： The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.
摘要翻译：本发明涉及一种用于测试快速集成数字电路，特别是半导体模块（例如SDRAM）的系统。为了在DDR-SDRAM的测试中实现必要的按时间顺序的精度，同时大规模生产所需的测试系统的高度并行性，将额外的半导体电路模块（BOST模块）插入到信号中标准测试设备和要测试的SDRAM之间的路径。该附加模块被设置为乘以常规测试设备的相对较慢的时钟频率，并且根据测试信号来确定用于测试SDRAM模块的控制信号，地址和数据背景的信号序列设备以及在测试前编程的寄存器内容，在BOST模块中。

10. 发明授权

US07117403B2 Method and device for generating digital signal patterns 有权
公开(公告)号：US07117403B2
公开(公告)日：2006-10-03
申请号：US09907777
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： G11C29/00 , G06F11/00 , G01R31/28
CPC分类号： G11C29/10 , G01R31/3183
摘要： The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.

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