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1. 发明授权

US07616573B2 Fair WRED for TCP UDP traffic mix 失效
标题翻译：公平WRED用于TCP UDP流量混合
公开(公告)号：US07616573B2
公开(公告)日：2009-11-10
申请号：US10864365
申请日：2004-06-10
申请人： Wladyslaw Olesinski , Steve Driediger
发明人： Wladyslaw Olesinski , Steve Driediger
IPC分类号： H04L12/26
CPC分类号： H04L47/10 , H04L47/12 , H04L47/193 , H04L47/196 , H04L47/2441 , H04L47/2475 , H04L47/326 , H04L47/6215 , H04L47/6225
摘要： A Weighted Random Early Detection (WRED) algorithm is described. The WRED algorithm provides fairness to responsive TCP and non-responsive UDP traffic at a buffer of a communications system. Because TCP traffic is responsive to congestion occurrences while UDP traffic is not, without controls, UDP will monopolize the buffer bandwidth. This invention solves the problem by applying congestion control alogrithms to TCP and UDP traffic separately. Discard thresholds for UDP traffic are dynamically modified in a manner that limits UDP traffic to a provisioned percentage of the buffer's available bandwidth, while a traditional WRED algorithm is applied to TCP traffic.
摘要翻译：描述了加权随机早期检测（WRED）算法。 WRED算法在通信系统的缓冲器处提供对响应的TCP和非响应UDP流量的公平性。由于TCP流量响应于拥塞发生，而UDP流量不受控制，UDP将垄断缓冲区带宽。本发明通过分别对TCP和UDP流量应用拥塞控制算法来解决问题。 UDP流量的丢弃阈值以将UDP流量限制为缓冲区可用带宽的提供百分比的方式进行动态修改，而将传统的WRED算法应用于TCP流量。

2. 发明申请

US20050276221A1 Fair WRED for TCP and UDP traffic mix 失效
标题翻译：公平WRED用于TCP和UDP流量混合
公开(公告)号：US20050276221A1
公开(公告)日：2005-12-15
申请号：US10864365
申请日：2004-06-10
申请人： Wladyslaw Olesinski , Steve Driediger
发明人： Wladyslaw Olesinski , Steve Driediger
IPC分类号： H04L12/56 , H04L1/00 , G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L12/26
CPC分类号： H04L47/10 , H04L47/12 , H04L47/193 , H04L47/196 , H04L47/2441 , H04L47/2475 , H04L47/326 , H04L47/6215 , H04L47/6225
摘要： A Weighted Random Early Detection (WRED) algorithm is described. The WRED algorithm provides fairness to responsive TCP and non-responsive UDP traffic at a buffer of a communications system. Because TCP traffic is responsive to congestion occurrences while UDP traffic is not, without controls, UDP will monopolize the buffer bandwidth. This invention solves the problem by applying congestion control alogrithms to TCP and UDP traffic separately. Discard thresholds for UDP traffic are dynamically modified in a manner that limits UDP traffic to a provisioned percentage of the buffer's available bandwidth, while a traditional WRED algorithm is applied to TCP traffic.
摘要翻译：描述了加权随机早期检测（WRED）算法。 WRED算法在通信系统的缓冲器处提供对响应的TCP和非响应UDP流量的公平性。由于TCP流量响应于拥塞发生，而UDP流量不受控制，UDP将垄断缓冲区带宽。本发明通过分别对TCP和UDP流量应用拥塞控制算法来解决问题。 UDP流量的丢弃阈值以将UDP流量限制为缓冲区可用带宽的提供百分比的方式进行动态修改，而将传统的WRED算法应用于TCP流量。

3. 发明授权

US07288969B1 Zero clock delay metastability filtering circuit 失效
标题翻译：零时钟延迟亚稳态滤波电路
公开(公告)号：US07288969B1
公开(公告)日：2007-10-30
申请号：US11397570
申请日：2006-04-05
申请人： Todd Richard Sleigh , Steve Driediger
发明人： Todd Richard Sleigh , Steve Driediger
IPC分类号： H03K5/22
CPC分类号： H03K5/135 , H03K5/1252
摘要： A metastability filtering circuit comprising: a sampling circuit for sampling a first clock signal with a second clock signal to produce a sampled first clock signal, the first clock signal being synchronous to an interface between first and second systems; an edge detection circuit coupled to the sampling circuit for receiving the sampled first clock signal and for producing a rate adapted first clock signal; a delay circuit coupled to the edge detection circuit for receiving the rate adapted first clock signal and for producing first and second clock enable signals, the second clock enable signal being a delayed version of the first clock enable signal; and, a shift register clocked by the second clock signal and having first and second sequential registers enabled by the first and second clock enable signals, respectively, for receiving an input signal from the first system at the first register and providing a filtered output signal to the second system from the second register, wherein the filtered output signal is provided within one cycle of the first clock signal thereby providing zero clock delay between the input and filtered output signals.
摘要翻译：一种亚稳态滤波电路，包括：采样电路，用于利用第二时钟信号对第一时钟信号进行采样，以产生采样的第一时钟信号，所述第一时钟信号与第一和第二系统之间的接口同步; 边缘检测电路，耦合到所述采样电路，用于接收采样的第一时钟信号并产生速率适配的第一时钟信号; 耦合到边缘检测电路的延迟电路，用于接收速率适配的第一时钟信号并产生第一和第二时钟使能信号，第二时钟使能信号是第一时钟使能信号的延迟版本; 以及分别由第二时钟信号计时并具有由第一和第二时钟使能信号使能的第一和第二顺序寄存器的移位寄存器，用于在第一寄存器处接收来自第一系统的输入信号，并将经滤波的输出信号提供给来自第二寄存器的第二系统，其中在第一时钟信号的一个周期内提供经滤波的输出信号，从而在输入和滤波的输出信号之间提供零时钟延迟。

4. 发明申请

US20060132190A1 Periodic electrical signal frequency monitoring systems and methods 有权
标题翻译：定期电信号频率监测系统及方法
公开(公告)号：US20060132190A1
公开(公告)日：2006-06-22
申请号：US11024332
申请日：2004-12-22
申请人： Steve Driediger , Dion Pike
发明人： Steve Driediger , Dion Pike
IPC分类号： H03K9/06
CPC分类号： G01R23/005 , G01R23/10
摘要： Systems and methods for monitoring frequencies of periodic electrical signals are disclosed. According to one technique, a first and second counters are respectively clocked by a first periodic electrical signal to be monitored and a second periodic electrical, and a threshold detector resets one of the counters when a count of the other counter crosses a reset threshold and determines whether a frequency error has occurred based on whether a count of the one of the counters crosses an alarm threshold. Another technique according to an embodiment of the invention also involves clocking counters with respective periodic electrical signals, although error detection is based on whether the counts of the counters cross respective associated thresholds in other than a particular sequence with respect to each other.
摘要翻译：公开了用于监视周期性电信号的频率的系统和方法。根据一种技术，第一和第二计数器分别由待监控的第一周期性电信号和第二周期性电信号定时，并且当另一个计数器的计数跨越复位阈值时，阈值检测器复位其中一个计数器，并且确定基于一个计数器的计数是否跨越警报阈值，是否发生频率错误。根据本发明的实施例的另一技术还涉及具有相应的周期性电信号的时钟计数器，尽管错误检测基于计数器的计数是否相对于彼此在特定序列之外跨相关相关阈值。

5. 发明申请

US20060156154A1 Addressing error and address detection systems and methods 有权
标题翻译：寻址错误和地址检测系统和方法
公开(公告)号：US20060156154A1
公开(公告)日：2006-07-13
申请号：US11024119
申请日：2004-12-22
申请人： Steve Driediger
发明人： Steve Driediger
IPC分类号： H03M13/00 , H04L1/00 , G06F11/00 , G08C25/00 , G06F11/30
CPC分类号： G06F11/0751 , G06F11/073 , G06F11/267 , G11C29/024
摘要： Addressing error detection systems and methods are disclosed. A target address is written to a memory in an electronic system and subsequently output on an address path through which the memory is addressable. An addressing error is detected by determining whether the target address output on the address path is detected at the memory. Address detection at the memory involves storing the target address, monitoring the address path for the target address, and providing an address detection indication based on whether the target address is detected on the address path. The address detection indication may be provided, for example, by setting a flag in a data structure which is stored in the memory.
摘要翻译：公开了寻址错误检测系统和方法。将目标地址写入电子系统中的存储器，然后在存储器可寻址的地址路径上输出。通过确定在存储器处是否检测到在地址路径上输出的目标地址来检测寻址错误。在存储器处的地址检测涉及存储目标地址，监视目标地址的地址路径，并且基于在地址路径上是否检测到目标地址来提供地址检测指示。可以例如通过设置存储在存储器中的数据结构中的标志来提供地址检测指示。

6. 发明授权

US06771605B1 Method and apparatus for providing integral cell payload integrity verification and detecting defective modules in telecommunication devices 失效
标题翻译：用于提供整体小区有效载荷完整性验证和检测电信设备中的有缺陷的模块的方法和装置
公开(公告)号：US06771605B1
公开(公告)日：2004-08-03
申请号：US09476374
申请日：2000-01-03
申请人： Randall Allan Law , Steven Douglas Margerm , Andre Poulin , Robert Morton , Steve Driediger , Jason Sterne , Paul Nadj
发明人： Randall Allan Law , Steven Douglas Margerm , Andre Poulin , Robert Morton , Steve Driediger , Jason Sterne , Paul Nadj
IPC分类号： H04L100
CPC分类号： H04L49/3081 , H04L49/30 , H04L49/3009 , H04L49/555 , H04L2012/5625 , H04L2012/5628 , H04L2012/5652 , H04Q11/0478
摘要： A method for identifying faulty modules within telecommunication devices, such as ATM switches, involves generating and attaching verification codes, such as CRC or checksum codes, to data packets, such as ATM cells, at an upstream location, determining the integrity of the verification codes at each of multiple downstream location within a telecommunication device; and signaling an error condition where a corrupted data packet has been detected. A verification code may be written to a filed of a data packet which is not used while the ATM cell is in transit through the telecommunication device, thereby identifying a faulty module device without adversely affecting throughput.
摘要翻译：用于识别诸如ATM交换机之类的电信设备内的故障模块的方法涉及在诸如ATM或ATM校验码之类的诸如CRC或校验和码之类的校验码生成和附加，确定验证码的完整性在电信设备内的多个下游位置的每个处; 并发出已经检测到损坏的数据分组的错误状况。当ATM信元通过电信设备进行传输时，验证码可以被写入到不使用的数据包的字段中，从而识别错误的模块设备而不会不利地影响吞吐量。

7. 发明授权

US07154305B2 Periodic electrical signal frequency monitoring systems and methods 有权
公开(公告)号：US07154305B2
公开(公告)日：2006-12-26
申请号：US11024332
申请日：2004-12-22
申请人： Steve Driediger , Dion Pike
发明人： Steve Driediger , Dion Pike
IPC分类号： G01R23/02
CPC分类号： G01R23/005 , G01R23/10
摘要： Systems and methods for monitoring frequencies of periodic electrical signals are disclosed. According to one technique, a first and second counters are respectively clocked by a first periodic electrical signal to be monitored and a second periodic electrical, and a threshold detector resets one of the counters when a count of the other counter crosses a reset threshold and determines whether a frequency error has occurred based on whether a count of the one of the counters crosses an alarm threshold. Another technique according to an embodiment of the invention also involves clocking counters with respective periodic electrical signals, although error detection is based on whether the counts of the counters cross respective associated thresholds in other than a particular sequence with respect to each other.

8. 发明授权

US07659757B2 Glitch-free clock regeneration circuit 有权
标题翻译：无毛刺时钟再生电路
公开(公告)号：US07659757B2
公开(公告)日：2010-02-09
申请号：US11711682
申请日：2007-02-28
申请人： Todd Sleigh , Steve Driediger
发明人： Todd Sleigh , Steve Driediger
IPC分类号： H03L7/00
CPC分类号： G06F1/04 , H03K5/1252
摘要： A clock regeneration circuit and method including an asynchronous clock signal input to a meta-stability filtering circuit, a synchronous clock signal input to the meta-stability filtering circuit with a frequency lower than the asynchronous clock signal, and being over-sampled and rate adapted to the asynchronous clock signal, an edge detector detecting an edge of the output of the meta-stability filtering circuit, a regenerated clock signal output therefrom, and a clock regeneration stage receiving an input that is the edge-detected output.
摘要翻译：一种包括输入到元稳定性滤波电路的异步时钟信号的时钟再生电路和方法，输入到低于异步时钟信号的频率的元稳定性滤波电路的同步时钟信号，并且被过采样和速率适配异步时钟信号，边缘检测器检测元稳定性滤波电路的输出的边沿，从其输出的再生时钟信号，以及接收作为边沿检测输出的输入的时钟再生级。

9. 发明申请

US20080204090A1 Glitch-free clock regeneration circuit 有权
标题翻译：无毛刺时钟再生电路
公开(公告)号：US20080204090A1
公开(公告)日：2008-08-28
申请号：US11711682
申请日：2007-02-28
申请人： Todd Sleigh , Steve Driediger
发明人： Todd Sleigh , Steve Driediger
IPC分类号： H03L7/06
CPC分类号： G06F1/04 , H03K5/1252
摘要： A clock regeneration circuit and method including an asynchronous clock signal input to a meta-stability filtering circuit, a synchronous clock signal input to the meta-stability filtering circuit with a frequency lower than the asynchronous clock signal, and being over-sampled and rate adapted to the asynchronous clock signal, an edge detector detecting an edge of the output of the meta-stability filtering circuit, a regenerated clock signal output therefrom, and a clock regeneration stage receiving an input that is the edge-detected output.
摘要翻译：一种包括输入到元稳定性滤波电路的异步时钟信号的时钟再生电路和方法，输入到低于异步时钟信号的频率的元稳定性滤波电路的同步时钟信号，并且被过采样和速率适配异步时钟信号，边缘检测器检测元稳定性滤波电路的输出的边沿，从其输出的再生时钟信号，以及接收作为边沿检测输出的输入的时钟再生级。

10. 发明申请

US20080062873A1 Credit-based rate control for high-speed interfaces 有权
标题翻译：基于信用的高速接口速率控制
公开(公告)号：US20080062873A1
公开(公告)日：2008-03-13
申请号：US11519559
申请日：2006-09-12
申请人： Daniel Semrad , Steve Driediger
发明人： Daniel Semrad , Steve Driediger
IPC分类号： H04L12/26
CPC分类号： H04L12/66
摘要： In accordance with at least one embodiment, credit-based flow control for high-speed interfaces is provided. Decoupling (separation) of high speed interface reference clocks from the interface data rates is enabled. Such decoupling allows consolidation of reference clocks used for high speed interfaces, thereby enabling one reference clock to be used for multiple interfaces having different data rates. It also results in reduced buffer resource (memory) requirements, and reduced system latency. In redundant systems it also simplifies the direct vs. spare selection mechanism.
摘要翻译：根据至少一个实施例，提供了用于高速接口的基于信用的流量控制。使能高速接口参考时钟与接口数据速率的分离（分离）。这种去耦允许合并用于高速接口的参考时钟，从而使一个参考时钟可用于具有不同数据速率的多个接口。它还会减少缓冲资源（内存）需求，并减少系统延迟。在冗余系统中，它也简化了直接与备用选择机制。

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