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1. 发明授权

US07288969B1 Zero clock delay metastability filtering circuit 失效
标题翻译：零时钟延迟亚稳态滤波电路
公开(公告)号：US07288969B1
公开(公告)日：2007-10-30
申请号：US11397570
申请日：2006-04-05
申请人： Todd Richard Sleigh , Steve Driediger
发明人： Todd Richard Sleigh , Steve Driediger
IPC分类号： H03K5/22
CPC分类号： H03K5/135 , H03K5/1252
摘要： A metastability filtering circuit comprising: a sampling circuit for sampling a first clock signal with a second clock signal to produce a sampled first clock signal, the first clock signal being synchronous to an interface between first and second systems; an edge detection circuit coupled to the sampling circuit for receiving the sampled first clock signal and for producing a rate adapted first clock signal; a delay circuit coupled to the edge detection circuit for receiving the rate adapted first clock signal and for producing first and second clock enable signals, the second clock enable signal being a delayed version of the first clock enable signal; and, a shift register clocked by the second clock signal and having first and second sequential registers enabled by the first and second clock enable signals, respectively, for receiving an input signal from the first system at the first register and providing a filtered output signal to the second system from the second register, wherein the filtered output signal is provided within one cycle of the first clock signal thereby providing zero clock delay between the input and filtered output signals.
摘要翻译：一种亚稳态滤波电路，包括：采样电路，用于利用第二时钟信号对第一时钟信号进行采样，以产生采样的第一时钟信号，所述第一时钟信号与第一和第二系统之间的接口同步; 边缘检测电路，耦合到所述采样电路，用于接收采样的第一时钟信号并产生速率适配的第一时钟信号; 耦合到边缘检测电路的延迟电路，用于接收速率适配的第一时钟信号并产生第一和第二时钟使能信号，第二时钟使能信号是第一时钟使能信号的延迟版本; 以及分别由第二时钟信号计时并具有由第一和第二时钟使能信号使能的第一和第二顺序寄存器的移位寄存器，用于在第一寄存器处接收来自第一系统的输入信号，并将经滤波的输出信号提供给来自第二寄存器的第二系统，其中在第一时钟信号的一个周期内提供经滤波的输出信号，从而在输入和滤波的输出信号之间提供零时钟延迟。

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