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1. 发明授权

US08830656B2 High density capacitor 有权
标题翻译：高密度电容器
公开(公告)号：US08830656B2
公开(公告)日：2014-09-09
申请号：US13149849
申请日：2011-05-31
申请人： Wim Besling , Klaus Reimann
发明人： Wim Besling , Klaus Reimann
IPC分类号： H01G9/02 , H01G9/04 , H01G9/145 , H01G9/28 , H01G9/042 , H01M10/0525
CPC分类号： H01G9/042 , H01G9/28 , H01M10/0525 , Y10T29/43
摘要： A high density capacitor 12, a method of manufacturing it, and applications of it are described. The capacitor 12 is an electrochemical capacitor using a metal ion accepting cathode 22 and a metal ion accepting anode 26 and a amorphous solid electrolyte 24 between. The cathode and anode may be of amorphous lithium ion intercalating material such as suitable transition metal oxides with multiple oxidation states.
摘要翻译：对高密度电容器12，其制造方法及其应用进行说明。电容器12是使用金属离子接受阴极22和金属离子接受阳极26以及非晶态固体电解质24之间的电化学电容器。阴极和阳极可以是非晶锂离子插层材料，例如具有多种氧化态的合适的过渡金属氧化物。

2. 发明申请

US20110292574A1 HIGH DENSITY CAPACITOR 有权
标题翻译：高密度电容器
公开(公告)号：US20110292574A1
公开(公告)日：2011-12-01
申请号：US13149849
申请日：2011-05-31
申请人： Wim Besling , Klaus Reimann
发明人： Wim Besling , Klaus Reimann
IPC分类号： H01G9/04 , H01G7/00
CPC分类号： H01G9/042 , H01G9/28 , H01M10/0525 , Y10T29/43
摘要： A high density capacitor 12, a method of manufacturing it, and applications of it are described. The capacitor 12 is an electrochemical capacitor using a metal ion accepting cathode 22 and a metal ion accepting anode 26 and a amorphous solid electrolyte 24 between. The cathode and anode may be of amorphous lithium ion intercalating material such as suitable transition metal oxides with multiple oxidation states.
摘要翻译：对高密度电容器12，其制造方法及其应用进行说明。电容器12是使用金属离子接受阴极22和金属离子接受阳极26以及非晶态固体电解质24之间的电化学电容器。阴极和阳极可以是非晶锂离子插层材料，例如具有多种氧化态的合适的过渡金属氧化物。

3. 发明授权

US07928006B2 Structure for a semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体器件的结构及其制造方法
公开(公告)号：US07928006B2
公开(公告)日：2011-04-19
申请号：US12066704
申请日：2006-09-08
申请人： Wim Besling
发明人： Wim Besling
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76823 , H01L21/76807 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76867
摘要： There is described a method of manufacturing a damascene interconnect (1) for a semiconductor device. A non conductive diffusion barrier (10) is formed over the wall(s) of a passage (7) defined by a porous low K di-electric material (6) and over the surface of a copper region (3) that closes one end of the passage (7). The non-conductive barrier layer (10) is plasma treated to transform an upper portion thereof (10b) into a conductive layer, while a low portion thereof (10a) comprising material that has penetrated pores of the di-electric material remains non-conductive. The passage (7) is then filled with a second copper region (13) forming an electrical interconnect with the first copper region (3) via the now conductive upper portion (1Ob) of the barrier (10). As a person skilled in the art will know, all embodiments of the invention described and claimed in this document may be combined without departing from the scope of the invention.
摘要翻译：描述了制造用于半导体器件的镶嵌互连（1）的方法。在由多孔低K二电极材料（6）限定的通道（7）的壁上形成非导电扩散阻挡层（10），并且在封闭一端的铜区域（3）的表面之上的通道（7）。不导电阻挡层（10）被等离子体处理以将其上部（10b）转变成导电层，而其中包含穿过二电极材料的孔的材料的低部分（10a）保持不导电。通道（7）然后通过屏障（10）的现在的导电上部分（10b）填充与第一铜区域（3）形成电互连的第二铜区域（13）。如本领域技术人员将知道的，在不脱离本发明的范围的情况下，可以组合在本文中描述和要求保护的本发明的所有实施例。

4. 发明申请

US20090218699A1 METAL INTERCONNECTS IN A DIELECTRIC MATERIAL 有权
标题翻译：电介质材料中的金属互连
公开(公告)号：US20090218699A1
公开(公告)日：2009-09-03
申请号：US12280978
申请日：2007-02-26
申请人： Joaquin Torres , Vincent Arnal , Laurent-Georges Gosset , Wim Besling
发明人： Joaquin Torres , Vincent Arnal , Laurent-Georges Gosset , Wim Besling
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76844
摘要： A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.
摘要翻译：半导体器件包括具有导电部分和由第一介电材料制成的电介质层的互连。在电介质层中形成沟槽。去除形成沟槽侧壁的电介质层的露出部分。然后将电介质衬垫沉积在沟槽的侧壁上，衬垫由第二电介质材料制成。

5. 发明申请

US20090197405A1 METHOD OF FORMING A LAYER OVER A SURFACE OF A FIRST MATERIAL EMBEDDED IN A SECOND MATERIAL IN A STRUCTURE FOR A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件结构中嵌入第二材料中的第一材料的表面上形成层的方法
公开(公告)号：US20090197405A1
公开(公告)日：2009-08-06
申请号：US12096231
申请日：2006-12-04
申请人： Wim Besling , Sonarith Chhun
发明人： Wim Besling , Sonarith Chhun
IPC分类号： H01L21/768
CPC分类号： H01L21/76849 , H01L21/28562 , H01L21/76801 , H01L21/76826 , H01L21/76828
摘要： There is described a method of forming a barrier layer (6, 110) over a surface of a copper line (3, 107) embedded in a dielectric material (2, 100) in an interconnect structure for a semiconductor device. The barrier layer (6, 110) is selectively deposited over the surface of the copper line (3, 107) by a vapour deposition step and the surface of the dielectric material (2, 100) is treated prior to the vapour deposition step to inhibit deposition of the barrier layer (6, 110) there on during the vapour deposition step. Preferably, the vapour deposition step comprises atomic layer deposition.
摘要翻译：描述了在半导体器件的互连结构中嵌入在电介质材料（2,100）中的铜线（3,107）的表面上形成阻挡层（6,110）的方法。通过气相沉积步骤在铜线（3,107）的表面上选择性地沉积阻挡层（6,110），并且在气相沉积步骤之前处理电介质材料（2,100）的表面以抑制在气相沉积步骤期间在其上沉积阻挡层（6,110）。优选地，气相沉积步骤包括原子层沉积。

6. 发明申请

US20080251921A1 Structure for a Semiconductor Device and a Method of Manufacturing the Same 有权
标题翻译：半导体器件的结构及其制造方法
公开(公告)号：US20080251921A1
公开(公告)日：2008-10-16
申请号：US12066704
申请日：2006-09-08
申请人： Wim Besling
发明人： Wim Besling
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76823 , H01L21/76807 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76867
摘要： There is described a method of manufacturing a damascene interconnect (1) for a semiconductor device. A non conductive diffusion barrier (10) is formed over the wall(s) of a passage (7) defined by a porous low K di-electric material (6) and over the surface of a copper region (3) that closes one end of the passage (7). The non-conductive barrier layer (10) is plasma treated to transform an upper portion thereof (10b) into a conductive layer, while a low portion thereof (10a) comprising material that has penetrated pores of the di-electric material remains non-conductive. The passage (7) is then filled with a second copper region (13) forming an electrical interconnect with the first copper region (3) via the now conductive upper portion (1Ob) of the barrier (10). As a person skilled in the art will know, all embodiments of the invention described and claimed in this document may be combined without departing from the scope of the invention.
摘要翻译：描述了制造用于半导体器件的镶嵌互连（1）的方法。在由多孔低K二电极材料（6）限定的通道（7）的壁上形成非导电扩散阻挡层（10），并且在封闭一端的铜区域（3）的表面之上的通道（7）。不导电阻挡层（10）被等离子体处理以将其上部（10b）转变成导电层，而其中包含穿过二电极材料的孔的材料的低部分（10a）保持不变导电。通道（7）然后通过阻挡层（10）的现在的导电上部分（10b）填充与第一铜区域（3）形成电互连的第二铜区域（13）。如本领域技术人员将知道的，在不脱离本发明的范围的情况下，可以组合在本文中描述和要求保护的本发明的所有实施例。

7. 发明授权

US07867889B2 Method of forming an interconnect structure on an integrated circuit die 有权
标题翻译：在集成电路管芯上形成互连结构的方法
公开(公告)号：US07867889B2
公开(公告)日：2011-01-11
申请号：US11720748
申请日：2005-11-24
申请人： Wim Besling
发明人： Wim Besling
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76823 , H01L21/76834 , H01L21/76867
摘要： A method of forming an interconnect structure, comprising forming a first interconnect layer (123) embedded in a first dielectric layer (118), forming a dielectric tantalum nitride barrier (150) by means of atomic layer deposition on the surface of the first interconnect (123), depositing a second dielectric layer (134) over the first interconnect (123) and the barrier (150) and etching a via (154) in the dielectric layer (134) to the barrier (150). The barrier (150) is then exposed to a treatment through the via (154) to change it from the dielectric phase to the conductive phase (180) and the via (154) is subsequently filled with conductive material (123).
摘要翻译：一种形成互连结构的方法，包括形成嵌入在第一介电层（118）中的第一互连层（123），通过在第一互连表面上的原子层沉积形成电介质氮化钽屏障（150）在第一互连（123）和屏障（150）上沉积第二电介质层（134），并将电介质层（134）中的通孔（154）蚀刻到屏障（150）上。然后，通过通孔（154）将阻挡层（150）暴露于处理，以将其从介电相改变为导电相（180），并且通孔（154）随后用导电材料（123）填充。

8. 发明申请

US20080311739A1 Method of Forming a Self Aligned Copper Capping Layer 审中-公开
标题翻译：形成自对准铜盖层的方法
公开(公告)号：US20080311739A1
公开(公告)日：2008-12-18
申请号：US12095142
申请日：2006-11-27
申请人： Wim Besling , Thomas Vanypre
发明人： Wim Besling , Thomas Vanypre
IPC分类号： H01L21/4763
CPC分类号： H01L23/53295 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76867 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of forming a capping layer on a copper interconnect line (14). The method comprises providing a layer (20) of Aluminium over the interconnect line (14) and the dielectric layer (10) in which it is embedded. This may be achieved by deposition or chemical exposure. The structure is then subjected to a process, such as annealing or further chemical exposure, in an environment containing, for example, Nitrogen atoms, so as to cause indiffusion of Al into the copper line (14) and nitridation to form a diffusion barrier 26 of the intermetallic compound CuAlN.
摘要翻译：一种在铜互连线（14）上形成覆盖层的方法。所述方法包括在所述互连线（14）上设置铝层（20）和所述电介质层（10）。这可以通过沉积或化学暴露来实现。然后在包含例如氮原子的环境中对该结构进行诸如退火或进一步的化学暴露的处理，以使Al向铜线（14）中扩散并进行氮化以形成扩散阻挡层26 的金属间化合物CuAlN。

9. 发明授权

US08349726B2 Method for fabricating a structure for a semiconductor device using a halogen based precursor 有权
标题翻译：使用卤素前体制造半导体器件的结构的方法
公开(公告)号：US08349726B2
公开(公告)日：2013-01-08
申请号：US12067494
申请日：2006-09-15
申请人： Wim Besling
发明人： Wim Besling
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/28562 , H01L21/28556 , H01L21/76843 , H01L21/76877
摘要： There is described a method of fabricating a dual damascene structure for a semiconductor device. A halogen based pre-cursor is used during vapor deposition of a diffusion barrier layer in a trench or via formed in a substrate. Residual halogen from the deposition is allowed to remain on the barrier layer and is used to catalyse growth of a metal layer on the barrier layer to fill the trench or via.
摘要翻译：描述了制造用于半导体器件的双镶嵌结构的方法。在通过形成在衬底中的沟槽或通孔中的扩散阻挡层的气相沉积期间使用基于卤素的前置标记。来自沉积的残余卤素保留在阻挡层上，并用于催化阻挡层上的金属层的生长以填充沟槽或通孔。

10. 发明授权

US08138082B2 Method for forming metal interconnects in a dielectric material 有权
标题翻译：在电介质材料中形成金属互连的方法
公开(公告)号：US08138082B2
公开(公告)日：2012-03-20
申请号：US12280978
申请日：2007-02-26
申请人： Joaquin Torres , Vincent Arnal , Laurent-Georges Gosset , Wim Besling
发明人： Joaquin Torres , Vincent Arnal , Laurent-Georges Gosset , Wim Besling
IPC分类号： H01L21/4763
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76844
摘要： A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.
摘要翻译：半导体器件包括具有导电部分和由第一介电材料制成的电介质层的互连。在电介质层中形成沟槽。去除形成沟槽侧壁的电介质层的露出部分。然后将电介质衬垫沉积在沟槽的侧壁上，衬垫由第二电介质材料制成。

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