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1. 发明授权

US07629224B1 VLSI fabrication processes for introducing pores into dielectric materials 失效
标题翻译：用于将孔引入电介质材料的VLSI制造工艺
公开(公告)号：US07629224B1
公开(公告)日：2009-12-08
申请号：US11606340
申请日：2006-11-28
申请人： Willibrordus Gerardus Maria van den Hoek , Nerissa S. Draeger , Raashina Humayun , Richard S. Hill , Jianing Sun , Gary Ray
发明人： Willibrordus Gerardus Maria van den Hoek , Nerissa S. Draeger , Raashina Humayun , Richard S. Hill , Jianing Sun , Gary Ray
IPC分类号： H01L21/76
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/0234 , H01L21/02343 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/76807 , H01L21/7682 , H01L2221/1047 , Y10S438/96
摘要： Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.
摘要翻译：通过在预先形成的复合电介质层中引入孔来制备多孔电介质层。可以在阻挡材料，金属或其它导电材料沉积以形成金属化层之后产生孔。以这种方式，导电材料设置有在其上沉积的相对平滑的连续表面。

2. 发明授权

US07972976B1 VLSI fabrication processes for introducing pores into dielectric materials 有权
标题翻译：用于将孔引入电介质材料的VLSI制造工艺
公开(公告)号：US07972976B1
公开(公告)日：2011-07-05
申请号：US12606920
申请日：2009-10-27
申请人： Willibrordus Gerardus Maria van den Hoek , Nerissa S. Draeger , Raashina Humayun , Richard S. Hill , Jianing Sun , Gary William Ray
发明人： Willibrordus Gerardus Maria van den Hoek , Nerissa S. Draeger , Raashina Humayun , Richard S. Hill , Jianing Sun , Gary William Ray
IPC分类号： H01L21/4757
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/0234 , H01L21/02343 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/76807 , H01L21/7682 , H01L2221/1047 , Y10S438/96
摘要： Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.
摘要翻译：通过在预先形成的复合电介质层中引入孔来制备多孔电介质层。可以在阻挡材料，金属或其它导电材料沉积以形成金属化层之后产生孔。以这种方式，导电材料设置有在其上沉积的相对平滑的连续表面。

3. 发明授权

US07166531B1 VLSI fabrication processes for introducing pores into dielectric materials 失效
标题翻译：用于将孔引入电介质材料的VLSI制造工艺
公开(公告)号：US07166531B1
公开(公告)日：2007-01-23
申请号：US11050621
申请日：2005-01-31
申请人： Willibrordus Gerardus Maria van den Hoek , Nerissa S. Draeger , Raashina Humayun , Richard S. Hill , Jianing Sun , Gary William Ray
发明人： Willibrordus Gerardus Maria van den Hoek , Nerissa S. Draeger , Raashina Humayun , Richard S. Hill , Jianing Sun , Gary William Ray
IPC分类号： H01L21/4763 , H01L21/469
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/0234 , H01L21/02343 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/76807 , H01L21/7682 , H01L2221/1047 , Y10S438/96
摘要： Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.
摘要翻译：通过在预先形成的复合电介质层中引入孔来制备多孔电介质层。可以在阻挡材料，金属或其它导电材料沉积以形成金属化层之后产生孔。以这种方式，导电材料设置有在其上沉积的相对平滑的连续表面。

4. 发明授权

US06753250B1 Method of fabricating low dielectric constant dielectric films 有权
标题翻译：制备低介电常数介电膜的方法
公开(公告)号：US06753250B1
公开(公告)日：2004-06-22
申请号：US10171289
申请日：2002-06-12
申请人： Richard S. Hill , Willibrordus Gerardus Maria van den Hoek , Robert H. Havemann
发明人： Richard S. Hill , Willibrordus Gerardus Maria van den Hoek , Robert H. Havemann
IPC分类号： H01L214763
CPC分类号： H01L21/7682 , H01L2221/1047
摘要： Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a preformed layer of semiconductor to produce a porous semiconductor layer.
摘要翻译：通过在致密电介质的预先形成的层中引入小的垂直或柱状间隙来产生多孔电介质层。可以通过与用于在VLSI器件上形成金属线和其它特征的工艺不同的特殊工艺形成孔。此外，在特定层的平坦化处理已经完成之后可以产生柱状间隙。然后，在形成孔之后，通过沉积另一层材料来封盖它们。以这种方式，保护新的多孔层免于直接暴露于随后的平坦化工艺的压力。在替代实施例中，应用本文所述的方法将孔导入预制的半导体层以产生多孔半导体层。

5. 发明授权

US06995439B1 Method of fabricating low dielectric constant dielectric films 失效
标题翻译：制备低介电常数介电膜的方法
公开(公告)号：US06995439B1
公开(公告)日：2006-02-07
申请号：US10803234
申请日：2004-03-17
申请人： Richard S. Hill , Willibrordus Gerardus Maria van den Hoek , Robert H. Havemann
发明人： Richard S. Hill , Willibrordus Gerardus Maria van den Hoek , Robert H. Havemann
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/7682 , H01L2221/1047
摘要： Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a pre-formed layer of semiconductor to produce a porous semiconductor layer.
摘要翻译：通过在致密电介质的预先形成的层中引入小的垂直或柱状间隙来产生多孔电介质层。可以通过与用于在VLSI器件上形成金属线和其它特征的工艺不同的特殊工艺形成孔。此外，在特定层的平坦化处理已经完成之后可以产生柱状间隙。然后，在形成孔之后，通过沉积另一层材料来封盖它们。以这种方式，保护新的多孔层免于直接暴露于随后的平坦化工艺的压力。在替代实施例中，应用本文所述的工艺以将孔引入预成形的半导体层中以产生多孔半导体层。

6. 发明授权

US08470191B2 Topography reduction and control by selective accelerator removal 有权
公开(公告)号：US08470191B2
公开(公告)日：2013-06-25
申请号：US11890790
申请日：2007-08-06
申请人： Steven T. Mayer , Mark L. Rea , Richard S. Hill , Avishai Kepten , R. Marshall Stowell , Eric G. Webb
发明人： Steven T. Mayer , Mark L. Rea , Richard S. Hill , Avishai Kepten , R. Marshall Stowell , Eric G. Webb
IPC分类号： C23F1/02
CPC分类号： C25D17/14 , B23H5/08 , C25D5/02 , C25D5/06 , C25D5/08 , C25D5/34 , C25D7/123 , C25D17/001 , C25D17/06 , C25F3/16 , C25F3/30 , H01L21/02068 , H01L21/2885 , H01L21/32115 , H01L21/3212 , H01L21/32134 , H01L21/7684 , H01L21/76849 , H01L21/76877
摘要： Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

7. 发明授权

US08133797B2 Protective layer to enable damage free gap fill 有权
标题翻译：保护层使无损空隙填充
公开(公告)号：US08133797B2
公开(公告)日：2012-03-13
申请号：US12122614
申请日：2008-05-16
申请人： Bart van Schravendijk , Richard S. Hill , Wilbert van den Hoek , Harald te Nijenhuis
发明人： Bart van Schravendijk , Richard S. Hill , Wilbert van den Hoek , Harald te Nijenhuis
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , C23C16/045 , C23C16/401 , H01L21/76801
摘要： In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids or weak spots is provided. A protective layer is deposited to protect underlying features in regions of the substrate having lower feature density so that unwanted material may be removed from regions of the substrate having higher feature density. This protective layer may deposits thicker on a low density feature than on a high density feature and may be deposited using a PECVD process or low sputter/deposition ratio HDP CVD process. This protective layer may also be a metallic oxide layer that is resistant to fluorine etching, such as zirconium oxide (ZrO2) or aluminum oxide (Al2O3).
摘要翻译：可以填充高纵横比（通常至少6:1，例如7:1或更高），窄宽度（通常为0.13微米，例如0.1微米或更小）的间隙的原位半导体工艺，而不损坏底层特征和少量或者不提供空隙或弱点的发生。沉积保护层以保护具有较低特征密度的衬底区域中的底层特征，使得可以从具有较高特征密度的衬底的区域去除不需要的材料。该保护层可以在低密度特征上比在高密度特征上沉积更厚，并且可以使用PECVD工艺或低溅射/沉积比HDP CVD工艺沉积。该保护层也可以是耐氟蚀刻的金属氧化物层，例如氧化锆（ZrO 2）或氧化铝（Al 2 O 3）。

8. 发明申请

US20090286381A1 Protective Layer To Enable Damage Free Gap Fill 有权
标题翻译：保护层可以防止空隙填充
公开(公告)号：US20090286381A1
公开(公告)日：2009-11-19
申请号：US12122614
申请日：2008-05-16
申请人： Bart van Schravendijk , Richard S. Hill , Wilbert van den Hoek , Harald te Nijenhuis
发明人： Bart van Schravendijk , Richard S. Hill , Wilbert van den Hoek , Harald te Nijenhuis
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , C23C16/045 , C23C16/401 , H01L21/76801
摘要： In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids or weak spots is provided. A protective layer is deposited to protect underlying features in regions of the substrate having lower feature density so that unwanted material may be removed from regions of the substrate having higher feature density. This protective layer may deposits thicker on a low density feature than on a high density feature and may be deposited using a PECVD process or low sputter/deposition ratio HDP CVD process. This protective layer may also be a metallic oxide layer that is resistant to fluorine etching, such as zirconium oxide (ZrO2) or aluminum oxide (Al2O3).
摘要翻译：可以填充高纵横比（通常至少6:1，例如7:1或更高），窄宽度（通常为0.13微米，例如0.1微米或更小）的间隙的原位半导体工艺，而不损坏底层特征和少量或者不提供空隙或弱点的发生。沉积保护层以保护具有较低特征密度的衬底区域中的底层特征，使得可以从具有较高特征密度的衬底的区域去除不需要的材料。该保护层可以在低密度特征上比在高密度特征上沉积更厚，并且可以使用PECVD工艺或低溅射/沉积比HDP CVD工艺沉积。该保护层也可以是耐氟蚀刻的金属氧化物层，例如氧化锆（ZrO 2）或氧化铝（Al 2 O 3）。

9. 发明授权

US08795482B1 Selective electrochemical accelerator removal 有权
标题翻译：选择性电化学促进剂去除
公开(公告)号：US08795482B1
公开(公告)日：2014-08-05
申请号：US13572483
申请日：2012-08-10
申请人： Steven T. Mayer , Marshall R. Stowell , John S. Drewery , Richard S. Hill , Timothy M. Archer , Avishai Kepten
发明人： Steven T. Mayer , Marshall R. Stowell , John S. Drewery , Richard S. Hill , Timothy M. Archer , Avishai Kepten
IPC分类号： C25D5/02 , C25F3/16
CPC分类号： B23H5/08 , C25F3/16 , H01L21/02068 , H01L21/2885 , H01L21/32115 , H01L21/7684
摘要： Methods and apparatus are provided for planar metal plating on a workpiece having a surface with recessed regions and exposed surface regions; comprising the steps of: causing a plating accelerator to become attached to said surface including the recessed and exposed surface regions; selectively removing the plating accelerator from the exposed surface regions without performing substantial metal plating on the surface; and after removal of plating accelerator is at least partially complete, plating metal onto the surface, whereby the plating accelerator remaining attached to the surface increases the rate of metal plating in the recessed regions relative to the rate of metal plating in the exposed surface regions.
摘要翻译：提供了用于在具有凹陷区域和暴露表面区域的表面的工件上进行平面金属电镀的方法和装置; 包括以下步骤：使电镀加速器附着到包括凹入和暴露的表面区域的所述表面; 选择性地从暴露的表面区域去除电镀加速器，而不在表面上进行实质的金属电镀; 在去除电镀促进剂至少部分完成后，将金属镀在表面上，由此保持附着在表面上的电镀加速剂相对于露出的表面区域中的金属电镀速率增加凹陷区域中的金属电镀速率。

10. 发明授权

US08268154B1 Selective electrochemical accelerator removal 有权
标题翻译：选择性电化学促进剂去除
公开(公告)号：US08268154B1
公开(公告)日：2012-09-18
申请号：US12860787
申请日：2010-08-20
申请人： Steven T. Mayer , John S. Drewery , Richard S. Hill , Timothy M. Archer , Avishai Kepten
发明人： Steven T. Mayer , John S. Drewery , Richard S. Hill , Timothy M. Archer , Avishai Kepten
IPC分类号： C25D5/02
CPC分类号： B23H5/08 , C25F3/16 , H01L21/02068 , H01L21/2885 , H01L21/32115 , H01L21/7684
摘要： Methods and apparatus are provided for planar metal plating on a workpiece having a surface with recessed regions and exposed surface regions; comprising the steps of: causing a plating accelerator to become attached to said surface including the recessed and exposed surface regions; selectively removing the plating accelerator from the exposed surface regions without performing substantial metal plating on the surface; and after removal of plating accelerator is at least partially complete, plating metal onto the surface, whereby the plating accelerator remaining attached to the surface increases the rate of metal plating in the recessed regions relative to the rate of metal plating in the exposed surface regions.
摘要翻译：提供了用于在具有凹陷区域和暴露表面区域的表面的工件上进行平面金属电镀的方法和装置; 包括以下步骤：使电镀加速器附着到包括凹入和暴露的表面区域的所述表面; 选择性地从暴露的表面区域去除电镀加速器，而不在表面上进行实质的金属电镀; 在去除电镀促进剂至少部分完成后，将金属镀在表面上，由此保持附着在表面上的电镀加速剂相对于露出的表面区域中的金属电镀速率增加凹陷区域中的金属电镀速率。

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