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1. 发明授权

US06821026B2 Redundant configurable VCSEL laser array optical light source 有权
公开(公告)号：US06821026B2
公开(公告)日：2004-11-23
申请号：US10235435
申请日：2002-09-04
申请人： William T. Devine , Jeffrey A. Kash , John U. Knickerbocker , Steven P. Ostrander , Jeannine M. Trewhella , Ronald P. Luijten
发明人： William T. Devine , Jeffrey A. Kash , John U. Knickerbocker , Steven P. Ostrander , Jeannine M. Trewhella , Ronald P. Luijten
IPC分类号： G02B636
CPC分类号： H01S5/423 , H01S5/02248 , H01S5/02284
摘要： A redundant configurable VCSEL laser array optical light source which provides for integrating optical communications capabilities into manufacturing processes for a substrate or submount such as a silicon or ceramic substrate, a multi-chip module, a package board, backplane or similar component. Multiple, spatially proximate lasers and photodetectors are provided as part of an optical transmitter or receiver module to simplify assembly of the module, particularly alignment of a laser or photodetector to an optical fiber or waveguide. A feedback loop and control logic select those laser(s) or photodiodes(s) which are most strongly coupled to the transmission medium to produce the best signals. This approach greatly simplifies optical alignment, to improve yield and relax mechanical tolerances, leading to lower assembly costs and higher manufacturing yields.

2. 发明授权

US07883277B2 Interconnecting (mapping) a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array 有权
标题翻译：将二维光电（OE）器件阵列互连（映射）到一维波导阵列
公开(公告)号：US07883277B2
公开(公告)日：2011-02-08
申请号：US12117803
申请日：2008-05-09
申请人： Russell A. Budd , Punit P. Chiniwalla , John A. Guckenberger , Jeffrey A. Kash , Jeremy D. Schaub , Michael Tan , Jeannine M. Trewhella , Garry Trott
发明人： Russell A. Budd , Punit P. Chiniwalla , John A. Guckenberger , Jeffrey A. Kash , Jeremy D. Schaub , Michael Tan , Jeannine M. Trewhella , Garry Trott
IPC分类号： G02B6/36 , G02B6/255
CPC分类号： G02B6/43 , G02B6/42 , G02B6/4214 , G02B6/4246
摘要： For integrated circuits including circuit packaging and circuit communication technologies provision is made for a method of interconnecting or mapping a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array. Also provided is an arrangement for the interconnecting or mapping of a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array.
摘要翻译：对于包括电路封装和电路通信技术的集成电路，提供了将二维光电（OE）器件阵列互连或映射到一维波导阵列的方法。还提供了用于将二维光电（OE）器件阵列互连或映射到一维波导阵列的布置。

3. 发明授权

US07474815B2 Interconnecting (mapping) a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array 有权
标题翻译：将二维光电（OE）器件阵列互连（映射）到一维波导阵列
公开(公告)号：US07474815B2
公开(公告)日：2009-01-06
申请号：US11374777
申请日：2006-03-14
申请人： Russell A. Budd , Punit P. Chiniwalla , John A. Guckenberger , Jeffrey A. Kash , Jeremy D. Schaub , Michael Tan , Jeannine M. Trewhella , Garry Trott
发明人： Russell A. Budd , Punit P. Chiniwalla , John A. Guckenberger , Jeffrey A. Kash , Jeremy D. Schaub , Michael Tan , Jeannine M. Trewhella , Garry Trott
IPC分类号： G02B6/12
CPC分类号： G02B6/43 , G02B6/42 , G02B6/4214 , G02B6/4246
摘要： For integrated circuits including circuit packaging and circuit communication technologies provision is made for a method of interconnecting or mapping a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array. Also provided is an arrangement for the interconnecting or mapping of a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array.
摘要翻译：对于包括电路封装和电路通信技术的集成电路，提供了将二维光电（OE）器件阵列互连或映射到一维波导阵列的方法。还提供了用于将二维光电（OE）器件阵列互连或映射到一维波导阵列的布置。

4. 发明申请

US20080205817A1 INTERCONNECTING (MAPPING) A TWO-DIMENSIONAL OPTOELECTRONIC (OE) DEVICE ARRAY TO A ONE-DIMENSIONAL WAVEGUIDE ARRAY 有权
标题翻译：互连（映射）二维光电（OE）器件阵列到一维波形阵列
公开(公告)号：US20080205817A1
公开(公告)日：2008-08-28
申请号：US12117803
申请日：2008-05-09
申请人： Russell A. Budd , Punit P. Chiniwalla , John A. Guckenberger , Jeffrey A. Kash , Jeremy D. Schaub , Michael Tan , Jeannine M. Trewhella , Garry Trott
发明人： Russell A. Budd , Punit P. Chiniwalla , John A. Guckenberger , Jeffrey A. Kash , Jeremy D. Schaub , Michael Tan , Jeannine M. Trewhella , Garry Trott
IPC分类号： G02B6/12 , H01L33/00
CPC分类号： G02B6/43 , G02B6/42 , G02B6/4214 , G02B6/4246
摘要： For integrated circuits including circuit packaging and circuit communication technologies provision is made for a method of interconnecting or mapping a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array. Also provided is an arrangement for the interconnecting or mapping of a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array.
摘要翻译：对于包括电路封装和电路通信技术的集成电路，提供了将二维光电（OE）器件阵列互连或映射到一维波导阵列的方法。还提供了用于将二维光电（OE）器件阵列互连或映射到一维波导阵列的布置。

5. 发明授权

US07915064B2 Processing for overcoming extreme topography 有权
标题翻译：克服极端地形的处理
公开(公告)号：US07915064B2
公开(公告)日：2011-03-29
申请号：US12538515
申请日：2009-08-10
申请人： Guy A. Cohen , Steven A. Cordes , Sherif A. Goma , Joanna Rosner , Jeannine M. Trewhella
发明人： Guy A. Cohen , Steven A. Cordes , Sherif A. Goma , Joanna Rosner , Jeannine M. Trewhella
IPC分类号： H01L21/00 , H01L21/311
CPC分类号： H01L21/31051 , B81C1/00611 , B81C2201/0119 , H01L21/0272 , H01L21/0337 , H01L21/31053 , H01L21/31058 , H01L21/3212 , H01L21/76838
摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
摘要翻译：通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。

6. 发明授权

US06940165B2 Impedance matched electrical interconnect using dielectric compounds 失效
标题翻译：使用电介质化合物阻抗匹配电气互连
公开(公告)号：US06940165B2
公开(公告)日：2005-09-06
申请号：US10241403
申请日：2002-09-11
申请人： Modest M. Oprysko , Lei Shan , Jeannine M. Trewhella
发明人： Modest M. Oprysko , Lei Shan , Jeannine M. Trewhella
IPC分类号： H01L23/495 , H01L23/64 , H01L23/48
CPC分类号： H01L23/4952 , H01L23/645 , H01L24/48 , H01L24/49 , H01L2223/6627 , H01L2224/05599 , H01L2224/45099 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/1903 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： An improved electrical interconnect is formed wherein a dielectric material having a controllable characteristic is applied to at least a portion of the interconnect. The controllable characteristic of the dielectric material is selectively adjustable so that the impedance of the electrical interconnect is substantially matched to at least one impedance at first and second ends of the interconnect. In this manner, an electrical discontinuity between the first and second ends of the electrical interconnect is reduced, thereby improving an electrical performance of the interconnect.
摘要翻译：形成改进的电互连，其中具有可控特性的介电材料被施加到互连的至少一部分。电介质材料的可控特性可选择性地调节，使得电互连的阻抗基本上与互连的第一和第二端处的至少一个阻抗匹配。以这种方式，电互连的第一和第二端之间的电中断减小，从而提高互连的电性能。

7. 发明授权

US5495545A Method for extending bandwidth of large core fiber optic transmission links 失效
标题翻译：扩展大型核心光纤传输链路带宽的方法
公开(公告)号：US5495545A
公开(公告)日：1996-02-27
申请号：US328177
申请日：1994-10-24
申请人： Michael F. Cina , Dennis L. Karst , Modest M. Oprysko , Mark B. Ritter , Stephen L. Spanoudis , Jeannine M. Trewhella
发明人： Michael F. Cina , Dennis L. Karst , Modest M. Oprysko , Mark B. Ritter , Stephen L. Spanoudis , Jeannine M. Trewhella
IPC分类号： G02B6/42 , G02B6/36
CPC分类号： G02B6/4206
摘要： A method for making an optical fiber transmission apparatus for limiting the optical modes which were emitted from a source in such a way to impinge on an optical fiber to extract a high bandwidth from the fiber. The apparatus includes a lens or aperture to control the angle and distribution of light launched into the fiber. The apparatus achieves reproducibly high bandwidths in large core step-index optical fibers of short transmission length distances. The lens or aperture introduces light from the source into the fiber at an angle at which substantially no intermode delay occurs as the light propagates down the fiber. An integral fiber optic coupling assembly that includes an optical electronic component receptacle, the lens and/or aperture, and an optical fiber connector interface which provides low cost easy to manufacture assembly is also disclosed. A unitary plastic housing provides the function of a lens and mechanical reference or locating features for the light source and optical fiber.
摘要翻译：一种制造光纤传输装置的方法，用于限制从源发射的光模，以照射到光纤上以从光纤提取高带宽。该装置包括用于控制发射到光纤中的光的角度和分布的透镜或孔。该装置在具有短传输长度距离的大型核心阶跃折射率光纤中实现可重复的高带宽。透镜或光圈将光从光源引入光纤，其角度基本上不发生模式间延迟，因为光沿着光纤传播。还公开了一种包括光学电子部件插座，透镜和/或孔径以及提供低成本易于制造组装的光纤连接器接口的整体光纤耦合组件。单一的塑料外壳提供了一个透镜的功能，并为光源和光纤提供机械参考或定位功能。

8. 发明授权

US08603846B2 Processing for overcoming extreme topography 失效
标题翻译：克服极端地形的处理
公开(公告)号：US08603846B2
公开(公告)日：2013-12-10
申请号：US13024711
申请日：2011-02-10
申请人： Guy A. Cohen , Steven A. Cordes , Sherif A. Goma , Joanna Rosner , Jeannine M. Trewhella
发明人： Guy A. Cohen , Steven A. Cordes , Sherif A. Goma , Joanna Rosner , Jeannine M. Trewhella
IPC分类号： H01L21/00
CPC分类号： H01L21/31051 , B81C1/00611 , B81C2201/0119 , H01L21/0272 , H01L21/0337 , H01L21/31053 , H01L21/31058 , H01L21/3212 , H01L21/76838
摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
摘要翻译：通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。

9. 发明授权

US07336863B2 Apparatus and methods for integrally packaging optoelectronic devices, IC chips and optical transmission lines 有权
标题翻译：用于整体封装光电器件，IC芯片和光传输线的装置和方法
公开(公告)号：US07336863B2
公开(公告)日：2008-02-26
申请号：US11257904
申请日：2005-10-25
申请人： Guy Moshe Cohen , Fuad Elias Doany , Jeannine M. Trewhella
发明人： Guy Moshe Cohen , Fuad Elias Doany , Jeannine M. Trewhella
IPC分类号： G02B6/12
CPC分类号： B29D11/0075 , G02B6/42 , G02B6/4224 , G02B6/423 , G02B6/4249
摘要： Apparatus and methods for packaging optical communication devices include optical bench structures, such as silicon-optical benches (SiOB). An optical communications apparatus includes an optical bench comprising a substrate having an electrical turning via formed therein. An optoelectronic (OE) chip and integrated circuit (IC) chip are mounted on the optical bench and electrically connected using the electrical turning via. The electrical turning via extends in directions both perpendicular and transverse to a surface of the substrate such that the OE chip and IC chip can be mounted on perpendicular surfaces of the optical bench in close proximity and electrically connected using the electrical turning via. More specifically, the OE chip and IC chip are mounted on the optical bench such that a light-emitting or light-detecting surface of the OE chip is substantially perpendicular to a surface of the IC chip having contacts, and such that optical transmission lines that are mounted parallel to the substrate surface can be directly coupled to the OE chip.
摘要翻译：用于封装光通信设备的装置和方法包括光学台架结构，例如硅光学台（SiOB）。一种光通信设备包括一个光学台，包括一个具有形成在其中的电转通路的基板。光电（OE）芯片和集成电路（IC）芯片安装在光学平台上，并使用电动转向电路进行电气连接。电动转向通孔在垂直于基板表面的横向方向上延伸，使得OE芯片和IC芯片可以安装在光学平台的垂直表面上，并且使用电动转向电路进行电连接。更具体地，OE芯片和IC芯片安装在光学平台上，使得OE芯片的发光或光检测表面基本上垂直于具有触点的IC芯片的表面，并且使得光传输线平行于衬底表面安装可以直接耦合到OE芯片。

10. 发明授权

US06992255B2 Via and via landing structures for smoothing transitions in multi-layer substrates 有权
标题翻译：通过和通过着陆结构，用于平滑多层衬底中的过渡
公开(公告)号：US06992255B2
公开(公告)日：2006-01-31
申请号：US10620733
申请日：2003-07-16
申请人： Modest Oprysko , Lei Shan , Jeannine M. Trewhella
发明人： Modest Oprysko , Lei Shan , Jeannine M. Trewhella
IPC分类号： H01R12/04 , H05K1/11
CPC分类号： H05K1/113 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2924/15173 , H01L2924/15174 , H01L2924/15311 , H01L2924/1903 , H01L2924/3011 , H05K1/0237 , H05K2201/09627 , H05K2201/09727 , H05K2201/0979
摘要： An integrated circuit arrangement or package includes a set of contact pads arranged in a pattern and a multi-layer conductive structure, which electrically connects the set of contact pads to at least one signal line. The conductive structure provides impedance matching between the pads and the at least one signal line.
摘要翻译：集成电路布置或封装包括以图案布置的一组接触焊盘和多层导电结构，其将该组接触焊盘电连接到至少一个信号线。导电结构提供焊盘和至少一个信号线之间的阻抗匹配。

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