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    • 1. 发明授权
    • System and method for synchronization of devices across a packet network
    • 通过分组网络同步设备的系统和方法
    • US07103072B1
    • 2006-09-05
    • US10326505
    • 2002-12-19
    • William SloanMark RumerMarcus Prewarski
    • William SloanMark RumerMarcus Prewarski
    • H04J3/06
    • H04J3/0685
    • A local time of a broadband loop carrier terminal is synchronized to a network time received from a source external to the broadband loop carrier terminal by comparing the local time to the network time to generate an error offset, and adjusting the local time based on the error offset. The network time may be received in response to a Network Time Protocol (NTP) poll transmitted by the broadband loop carrier terminal. In some cases, the poll is transmitted over a communication medium using an asynchronous packet protocol, such as Ethernet or TCP/IP. In one embodiment, the local time is based on the output of a local oscillator (e.g., a voltage controlled oscillator), the frequency of which may be adjusted using control logic which uses a filtered version of the error offset along with a factory calibration and/or temperature compensation to produce a control voltage to control the oscillator frequency.
    • 通过将本地时间与网络时间进行比较以产生误差偏移,并且基于误差来调整本地时间,宽带环路载波终端的本地时间与从宽带环路载波终端外部的源接收的网络时间同步 抵消。 可以响应于宽带环路载波终端发送的网络时间协议(NTP)轮询来接收网络时间。 在某些情况下,使用异步分组协议(例如以太网或TCP / IP)在通信介质上传输轮询。 在一个实施例中,本地时间基于本地振荡器(例如,压控振荡器)的输出,其频率可以使用控制逻辑来调整,该控制逻辑使用误差偏移的滤波版本以及工厂校准, /或温度补偿产生控制电压来控制振荡器频率。
    • 3. 发明授权
    • Free space optical “backplane” (FSO)
    • 自由空间光学“背板”(FSO)
    • US06526211B2
    • 2003-02-25
    • US09844896
    • 2001-04-26
    • Mark RumerRonald Jeffries
    • Mark RumerRonald Jeffries
    • G02B600
    • G02B6/43G02B6/4245G02B6/4284
    • A system having a free space optical transmission capability for data and/or control interconnection is described. Switch cards, having corresponding pairs of laser transmitters and photodetectors are placed in a chassis, at each end, facing each other. Each laser transmitter/photodetector (LTPD) pair of one switch card is targeted to a corresponding photodetector/laser transmitter (PDLT) pair of the other. System line cards have a LTPD pair on one side and a PDLT pair on the other side. A line card is positioned in the chassis so that the LTPD pair is aligned with a corresponding PDLT pair on one switch card and the PDLT pair is aligned with a corresponding LTPD pair on the other switch card. The line card may, therefore, communicate with either switch card. The line cards contain apertures so that communication between other line cards and the switch cards is not obstructed.
    • 描述了一种具有用于数据和/或控制互连的自由空间光传输能力的系统。 具有相应对的激光发射器和光电检测器的开关卡被放置在机架中,每个端部彼此面对。 每个激光发射器/光电检测器(LTPD)对的一个开关卡针对另一个相应的光电检测器/激光发射器(PDLT)对。 系统线卡在一侧有一个LTPD对,另一边有一个PDLT对。 线卡位于机箱中,使LTPD对与一个开关卡上相应的PDLT对对准,PDLT对与另一个开关卡上的相应LTPD对对齐。 因此,线卡可以与任一开关卡通信。 线卡包含孔,使得其他线卡和开关卡之间的通信不被阻塞。
    • 6. 发明授权
    • ATM switch with integrated system bus
    • ATM交换机带集成系统总线
    • US5898688A
    • 1999-04-27
    • US653259
    • 1996-05-24
    • Kenneth NortonMark Rumer
    • Kenneth NortonMark Rumer
    • H04L12/56H04Q11/04
    • H04L12/5601H04L49/107H04L49/3081H04Q11/0478H04L2012/5652H04L2012/5681
    • A network switch includes a plurality of cell processing units coupled together via a switch bus. In a preferred embodiment, the switch bus supports the peripheral component interconnect (PCI) bus protocol. Each cell processing unit includes a segmentation and reassembly unit (SAR), a RISC processor, a port processor, and a bus control unit. The SAR generates cells from frames of data stored in memory and transfers those cells to a destination mailbox in response to commands from from the RISC processor. The SAR assembles a cell within an internal register by combining cell header information with payload data read from memory. Once a cell has been assembled, it is sent to the bus controller for transmission across the switch bus to an address given by a mailbox number. Cells are transferred across the switch bus using a PCI burst write to the mailbox. A reassembly function gathers 48-byte cells into one or more larger output buffers. Cell reassembly is triggered by another RISC processor command. During reassembly, cell header information is discarded and the data payload bytes are read to an internal buffer within the SAR. The payload data is then written to a memory location pointed to by a buffer memory pointer. The switch bus 14 is also used for the transfer of control information between configuration registers of the cell processing units 12.
    • 网络交换机包括通过交换总线耦合在一起的多个小区处理单元。 在优选实施例中,交换总线支持外围组件互连(PCI)总线协议。 每个单元处理单元包括分段和重组单元(SAR),RISC处理器,端口处理器和总线控制单元。 SAR从存储在存储器中的数据帧生成单元,并根据来自RISC处理器的命令将这些单元传输到目标邮箱。 SAR通过将单元头信息与从存储器读取的有效载荷数据相结合,组合内部寄存器中的单元。 一旦单元组装完成,就将其发送到总线控制器,以便通过交换总线传输到由邮箱号码给出的地址。 使用对邮箱的PCI突发写入,单元通过交换总线传输。 重组功能将48字节的单元格收集到一个或多个较大的输出缓冲器中。 单元重组由另一个RISC处理器命令触发。 在重组期间,信元报头信息被丢弃,并且数据有效载荷字节被读取到SAR内的内部缓冲器。 然后将有效载荷数据写入缓冲存储器指针指向的存储单元。 开关总线14也用于在单元处理单元12的配置寄存器之间传送控制信息。
    • 9. 发明授权
    • ATM utopia bus snooper switch
    • US06618376B2
    • 2003-09-09
    • US09809600
    • 2001-03-14
    • Mark Rumer
    • Mark Rumer
    • H04L1228
    • H04Q11/0478H04L2012/5613H04L2012/5615
    • A communication bus snooper switch includes an inbound cell queue coupled to receive ATM cells from a number of ATM physical layer interfaces across a common inbound bus. An out-bound cell queue (which may be the same queue as the inbound cell queue when a dual port queue is used) is coupled to provide the ATM cells to separate ATM termination points according cell address information across separate out-bound busses. Each of the out-bound busses is associated with one of the ATM termination points. The snooper switch is configured to operate as an ATM bus master when communicating with the physical layer interfaces and as a ATM bus slave when communicating with the ATM termination points. During transmit operations, cells from the various ATM termination points are queued in corresponding transmission cell queues within the snooper switch and, thereafter, provided to the ATM physical layer interfaces according to an arbitration scheme implemented at the snooper switch.